FX2LP pauses for 125us during GPIF In Transfers

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RoWa_685396
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I'm using the FX2LP to read in info from an external FPGA which is mimicking a cameralink interface. I've got it working about 50% of the time but have an issue where the GPIF transfers will stop for 125us while something else is going on (not sure what but the USB micro frames are 125us and this may be a clue). I'm trying to load 1024 16 bit Words into the EP2InFIFO's from the FPGA. Below is a code snipet of the routine which starts the GPIF Burst Read routine. Right now I'm polling for it to be done and then arming the endpoint. This routine would be called 4 times to load the entire 4K bytes of data.  I've enabled a GPIF Crtl output line that I can monitor on the scope to see when its loading the FIFO and then have Port A1 pin toggling while in this routine to help me debug what is going on.

The issue is that I'm missing data that is coming from the FPGA. The FPGA is producing data at a relatively slow 1MHz rate. I've got the GPIF configured to read data in when the DataValid signal is high. From the attached scope pic this works most of the time (the green boxes). The issue is that it seems like the GPIF transfer process will hang randomly for 125us and then resume. From a code standpoint, since the PA1 pin is still toggling at the same rate the CPU is still in the routine below waiting for the FIFO to fill, however during this 125us period (the red boxes in the pic) its missing data. Any clue what may be causing the GPIF transfer to hang for 125us?

I've used similar routine like this before on other project and they all worked however in those cases the reads were at a much faster rate. Any help is appreciated.

BYTE Send_EP2_wordsBurst (WORD NumOfWords  ) 

{

BYTE a;

if ( WaitForEp_Full ( bmEP2FULL ))

return FALSE;

       EP2GPIFTCH = NumOfWords  >> 8;  //(GPIFTCB0) setup transaction count

       SYNCDELAY;                 

       EP2GPIFTCL = NumOfWords  & 0xff;

       SYNCDELAY;              

       if( !( EP2468STAT & bmEP2FULL ) )

          {

          a=EP2GPIFTRIG;          // trigger start of  read process

          while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit

               {

               IOA ^= 0x02;          //toggle pin to see whats going on

               }

          GPIFTRIG = GPIFTRIGRD | GPIF_EP2; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)

          }

     NumOfWords  *= 2 ; // convert to bytes

     EP2BCH = NumOfWords >> 8;      // load byte count to lock in packet

     SYNCDELAY;

     EP2BCL = NumOfWords & 0xff;

     SYNCDELAY;

return TRUE;

}

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1 Solution

Hello,

Please remove either one of the statements mentioned below from your routine as both will trigger the read operation .

a=EP2GPIFTRIG;

or

GPIFTRIG = GPIFTRIGRD | GPIF_EP2;

Best Regards,

Yatheesh

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3 Replies
YatheeshD_36
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

Hello,

Can you please let me know what is the source of interface clock for FX2LP, Internal or External?

If External IFCLK is used then the frequency should be between 5MHz and 48 MHz.

Best Regards,

Yatheesh

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I'm using the internal IFClk. I've tried 48 & 30MHz and then Synch and Asynch configurations and the issues still exists. Changing these details made slight difference on exactly when the data was latched in once the Data Valid line went high but, I'd still have the random 125us period where no transfers would exist.

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Hello,

Please remove either one of the statements mentioned below from your routine as both will trigger the read operation .

a=EP2GPIFTRIG;

or

GPIFTRIG = GPIFTRIGRD | GPIF_EP2;

Best Regards,

Yatheesh

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