SPI Slave Statusregister

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MaFl_1342516
Level 1
Level 1

Ich versuche ein SPI Slave auf einem PsoC5LP in betrieb zu nehmen.

Für die ersten Tests genügen mir die 4 Bytes des FIFO und der Polling-Betrieb.

Meiner Ansicht nach sind die Bits der Status-Register nicht entsprechend der Dokumentation und API.

Ohne das Daten übermittelt wurden, ergibt "SPI_ReadRxStatus()" 0x50 zurück.

Das heisst folgende Bits sind gesetzt:"Rx FIFO Full" und "Rx FIFO Empty" das geht doch gar nicht!

SPI_ReadTxStatus liefert zuerst 0x06 ("SPI_STS_TX_FIFO_NOT_FULL" und "SPI_STS_TX_FIFO_EMPTY").

Soweit so gut. Nachdem jedoch 4 Bytes mittels "SPI_PutArray(data,4)" geschrieben werden, liefert "SPI_ReadRxStatus()" den Wert 0x04 zurück .

Also "Tx Fifo Empty" aber nicht "Tx FIFO not Full". Das kann doch nicht sein!

Hat iergendjemand eine SPI SLAVE mit Abfrage der Statusregister in Betrieb?

Martin F.

Mein Beispiel mit SPI SLAVE

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Martin,

I've compiled your project with some modifications:

  • I've compiled for the CY8CKIT-059 device.
  • I've lowered the internal clock rate of the SPI_SOM component to 12KHz.
  • I've changed the clock source to the internal IMO clock of 24MHz.
  • Added the UART component for debugging dumps.
  • Disabled SPI_SOM_CLK and connected a 1KHz clock to the input.  (This is important to answer some of your questions).

Your statement:

Ohne das Daten übermittelt wurden, ergibt "SPI_ReadRxStatus()" 0x50 zurück.

Das heisst folgende Bits sind gesetzt:"Rx FIFO Full" und "Rx FIFO Empty" das geht doch gar nicht!

translation:

Without the data being transmitted, "SPI_ReadRxStatus ()" returns 0x50.

That means the following bits are set: "Rx FIFO Full" and "Rx FIFO Empty" that does not work!

You are generally correct.  FIFO Empty and Full at the same time doesn't make sense.  Hmm.  This should have been cleared during the component initialization phase.

Your statement:

SPI_ReadTxStatus liefert zuerst 0x06 ("SPI_STS_TX_FIFO_NOT_FULL" und "SPI_STS_TX_FIFO_EMPTY").

Soweit so gut. Nachdem jedoch 4 Bytes mittels "SPI_PutArray(data,4)" geschrieben werden, liefert "SPI_ReadRxStatus()" den Wert 0x04 zurück .

Also "Tx Fifo Empty" aber nicht "Tx FIFO not Full". Das kann doch nicht sein!

translation:

SPI_ReadTxStatus first returns 0x06 ("SPI_STS_TX_FIFO_NOT_FULL" and "SPI_STS_TX_FIFO_EMPTY").

So far so good. However, after 4 bytes are written using "SPI_PutArray (data, 4)", "SPI_ReadRxStatus ()" returns 0x04.

So "Tx Fifo Empty" but not "Tx FIFO not Full". This can not be!

The first SPI_ReadTxStatus() is correct.  If a FIFO is empty, it is also not full.  So both can be true.

The second SPI_ReadTxStatus() after the SPI_PutArray() is a little strange.  The SPI_PutArray() did put 4 bytes into the 4 byte FIFO.  Therefore, I agree, the txStatus should report a 0x00 which means SPI_STS_TX_FIFO_NOT_FULL and SPI_STS_TX_FIFO_EMPTY are both 0.

I've attached my modified version of your program.  Note: I added a clock to replace the SPI_SOM_CLK input.  This allows the SPI_Slave HW to properly clock input (MOSI) and output (MISO) data.  I get different rxStatus and txStatus when I do this.

Len

Len
"Engineering is an Art. The Art of Compromise."

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3 Replies
Hari
Moderator
Moderator
Moderator
750 replies posted 500 replies posted 250 solutions authored

HiMaFl_1342516

You can refer the SPI_Design for a sample project demonstrating SPI operation. Please attach your project so that we can have a look and debug any issues in the firmware.

best regards

Harigovind

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Projekt oben angefügt

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Martin,

I've compiled your project with some modifications:

  • I've compiled for the CY8CKIT-059 device.
  • I've lowered the internal clock rate of the SPI_SOM component to 12KHz.
  • I've changed the clock source to the internal IMO clock of 24MHz.
  • Added the UART component for debugging dumps.
  • Disabled SPI_SOM_CLK and connected a 1KHz clock to the input.  (This is important to answer some of your questions).

Your statement:

Ohne das Daten übermittelt wurden, ergibt "SPI_ReadRxStatus()" 0x50 zurück.

Das heisst folgende Bits sind gesetzt:"Rx FIFO Full" und "Rx FIFO Empty" das geht doch gar nicht!

translation:

Without the data being transmitted, "SPI_ReadRxStatus ()" returns 0x50.

That means the following bits are set: "Rx FIFO Full" and "Rx FIFO Empty" that does not work!

You are generally correct.  FIFO Empty and Full at the same time doesn't make sense.  Hmm.  This should have been cleared during the component initialization phase.

Your statement:

SPI_ReadTxStatus liefert zuerst 0x06 ("SPI_STS_TX_FIFO_NOT_FULL" und "SPI_STS_TX_FIFO_EMPTY").

Soweit so gut. Nachdem jedoch 4 Bytes mittels "SPI_PutArray(data,4)" geschrieben werden, liefert "SPI_ReadRxStatus()" den Wert 0x04 zurück .

Also "Tx Fifo Empty" aber nicht "Tx FIFO not Full". Das kann doch nicht sein!

translation:

SPI_ReadTxStatus first returns 0x06 ("SPI_STS_TX_FIFO_NOT_FULL" and "SPI_STS_TX_FIFO_EMPTY").

So far so good. However, after 4 bytes are written using "SPI_PutArray (data, 4)", "SPI_ReadRxStatus ()" returns 0x04.

So "Tx Fifo Empty" but not "Tx FIFO not Full". This can not be!

The first SPI_ReadTxStatus() is correct.  If a FIFO is empty, it is also not full.  So both can be true.

The second SPI_ReadTxStatus() after the SPI_PutArray() is a little strange.  The SPI_PutArray() did put 4 bytes into the 4 byte FIFO.  Therefore, I agree, the txStatus should report a 0x00 which means SPI_STS_TX_FIFO_NOT_FULL and SPI_STS_TX_FIFO_EMPTY are both 0.

I've attached my modified version of your program.  Note: I added a clock to replace the SPI_SOM_CLK input.  This allows the SPI_Slave HW to properly clock input (MOSI) and output (MISO) data.  I get different rxStatus and txStatus when I do this.

Len

Len
"Engineering is an Art. The Art of Compromise."
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