FIFO is needed for 10+MHz communication speed, you can use standard Control/Status registers for 1+MHz speed.
You can find a copy of the Brad Budlong's (AKA PSoC Sensei) 8/16-bit FIFOin component on this page, along with a demo project
You can find community FIFOout component on this page (I believe that it needs more testing)
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I haven't tackled FIFOin, but I made FIFOout work; I did end up rewriting all the verilog to make it work the way I wanted (the consumer raises a req line to indicate it wants data, the FIFO raises a rdy line to indicate data is available, and then nothing happens until the consumer drops the req line again). You can find it here: