Error: mpr.M0006: Datapath found without a clock. This is not allowed.

[CAAG_1860411]

Hello

I created a Verilog file where I have combinational logic. I generate a symbol, a Verilog file, and a Datapath, and I have registers of my hardware description file. But when I want to build my design, it shows me this error M0006, and I don't know how to fix it.

Thanks

[Ekta_N]

Hello Carlos,

Thank you for contacting Cypress Technical support.

Can you please attach a screenshot of the error window?

Can you please attach your project so that we reproduce the error at our side this will help us get better insight of the issue/

Best Regards

Ekta

[CAAG_1860411]

Hello Ektan.
I work with PSoC in my PhD with radiation effects. I need a majory voter in verilog. But I can't move forward with this error.

and

Thank you.

[MotooTanaka]

Hi,

Are you using clock inside the module?

Or how about modifying the line

assign T = ((a & b) | (b & c) | (c & a)) ;

To

  always @ (posedge clock) begin

      T <= ((a & b) | (b & c) | (c & a)) ;

   end

moto

[Ekta_N · Accepted solution]

Thank you for the input moto.

Carlos can you implement the changes suggested by moto.  The user clock drives the blocks in the UDB therefore you need to use clock for driving the logic in your project.

I have attached a project implementing the changes suggested by moto and the project is building fine.

Please have a look at it.

Thanks and Regards

Ekta