Modus 2.0 (CYBLE-416045-02): How to set target to run on CM0+

[user_1669321]

Hi,

I'm trying to setup a project that runs on the CM0+­. My first thought was to use the linker scripts from PSoC Creator and try to recreate what PSoC Creator does (compiling two projects - CM0+ and CM4 - and merging them before debugging), but it does not seem as straight forward.

Here are my steps:

1. Create a new "Empty PSoC6 App" project for the kit CY8CPROTO-063-BLE
2. Copy "cy8c6xx7_cm0plus.ld" from Creator into the workspace
3. In Makefile, add the path to the linker script in the variable LINKER_SCRIPT
4. In CY8CPROTO-063-BLE.mk, remove CM0P_SLEEP from the COMPONENTS variable
5. In ./libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/, delete startup_psoc6_01_cm4.S and add startup_psoc63_cm0plus.S from Creator

While that does build, I really have the impression that I'm missing some steps. Furthermore, when I try to debug, I get:

===== Cortex-M DWT registers

Error: psoc6.cpu.cm4 -- clearing lockup after double fault

Polling target psoc6.cpu.cm4 failed, trying to reexamine

Info : psoc6.cpu.cm4: hardware has 6 breakpoints, 4 watchpoints

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x8008f3f0

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0x8008f3f0

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xfffff000

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xfffff000

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xfffff000

Info : SWD DPIDR 0x6ba02477

Error: Failed to read memory at 0xfffff000

Has anyone been able to run code on the CM0+ using Modus, other than the prebuilt images?

Thanks,

Fred

[DheerajK_81 · Accepted solution]

As mentioned in your previous thread, ModusToolbox 2.0 doesn't officially support dual core application development.

However, it is doable. But please note that this isn't tested and there might be potention pitfalls since this is not supported in the current implementation of the tool.

Here's how it can be done. You need to create two applications one for the CM0p and other for the CM4 core.

For the CM0p Application:

Using ModuxToolbox 2.0 create the application targeting the BSP of interest. In the BSP (e.g. TARGET_CY8CPROTO-063-BLE) make the following edits.

1. Copy the CM0P linker script from PDL into the BSP.

copy

"libs/psoc6pdl/devices/bsp/COMPONENT_MTB/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld"

to

"libs/TARGET_CY8CPROTO-063-BLE/linker/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld"

2. Create the directories COMPONENT_CM0P and COMPONENT_CM4 in the BSP startup code create directories

libs/TARGET_CY8CPROTO-063-BLE/startup/COMPONENT_CM4

libs/TARGET_CY8CPROTO-063-BLE/startup/COMPONENT_CM0P

3. Move the CM4 C startup code from BSP into a COMPONENT_CM4 directory

move

libs/TARGET_CY8CPROTO-063-BLE/startup/system_psoc6_cm4.c

to

libs/TARGET_CY8CPROTO-063-BLE/startup/COMPONENT_CM4/system_psoc6_cm4.c

4. Copy the CM0P C startup code from PDL into the COMPONENT_CM0P directory

copy

libs/psoc6pdl/devices/bsp/COMPONENT_MTB/startup/system_psoc6_cm0plus.c

to

libs/TARGET_CY8CPROTO-063-BLE/startup/COMPONENT_CM0P/system_psoc6_cm0p.c

5. Create the directories COMPONENT_CM0P and COMPONENT_CM4 in the BSP startup assembly code create directories

libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/COMPONENT_CM4

libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/COMPONENT_CM0P

6. Move the CM4 assembly startup code into the COMPONENT_CM4 directory

move

libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S

to

libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/COMPONENT_CM4/startup_psoc6_01_cm4.S

7. Copy the CM0P assembly startup code from PDL into the BSP directory

copy

libs/psoc6pdl/devices/bsp/COMPONENT_MTB/startup/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S

to

libs/TARGET_CY8CPROTO-063-BLE/startup/TOOLCHAIN_GCC_ARM/COMPONENT_CM0P/startup_psoc6_01_cm0plus.S

8. Remove references to HAL, BSP, etc in the main.c. Keep only references to PDL and call init_cycfg_all() to perform configurator based initialization.

9. In the makefile for the BSP, you need to remove the CY_USING_HAL define.

edit

libs/TARGET_CY8CPROTO-063-BLE/CY8CPROTO-063-BLE.mk

and remove CY_USING_HAL from the defines line.

10.You will need to update the flash size for any CM0 application that does anything useful. This update will need to be in the CM0P linker script. This update must align

with the flash size and location set for the CM4 application.

libs/TARGET_CY8CPROTO-063-BLE/linker/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld

         ram               (rwx)   : ORIGIN = 0x08000000, LENGTH = 0x2000

         flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x2000

11. Now for the build system to use CM0P core specific folders you defined, you need to specify the default core in "defines.mk" in the directory: "libs\psoc6make\make\recipe\"

Change CM4 to CM0p

#

# Define the default core

#

CORE?=CM0P

For the CM4 Application:

Using ModusToolbox 2.0 create the application targeting the same BSP selected for the CM0P application. In the BSP (e.g. TARGET_CY8CPROTO-063-BLE) make the following edits. The edits here will just remove the default CM0P image from the CM4 build.

11.Edit the linker script to remove the CM0P image.

edit

libs/TARGET_CY8CPROTO-063-BLE/CY8CPROTO-063-BLE.mk

remove CM0P_SLEEP from the COMPONENTS variable

and change

• the start flash address in the MEMORY section to where the CM4 image will be placed. Keep in mind that this must be aligned on a 1024 byte boundary since this is where the vector table will be placed. I reserved 8K for the CM0 application and used the line below for the CM4 flash in the linker script.

                                       ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0x45800

                                       flash             (rx)    : ORIGIN = 0x10002000, LENGTH = 0xFE000

• Remove the linker script code in the SECTIONS part of the file related to the CM0P image.

      /* Cortex-M0+ application flash image area */

      .cy_m0p_image ORIGIN(flash) :

      {

           . = ALIGN(4);

           __cy_m0p_code_start = . ;

           KEEP(*(.cy_m0p_image))

           __cy_m0p_code_end = . ;

      } > flash

      /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */

      ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4,

     increase FLASH_CM0P_SIZE")

Add code to main.c of CM0p Application to enable CM4 and for any other task intended. Both the application should be able to build and program. Note that you need to program CM0p Application first or else the CM4 application won't be able to run.

But again, this is more of a tweak and I would recommend waiting for the next release of ModusToolbox where we plan to re-enable dual core development.

Regards,
Dheeraj

[user_1669321]

Thanks a lot for the answer, Dheeraj! It is very informative.

As you said, we will wait for official support on this matter. It's best to use tested tools.

I do have a question, though. Why do we need to remove CY_USING_HAL? Is the HAL currently only supporting the CM4?

Thanks a lot!

[DheerajK_81]

I think yes, but haven't tested it. A KBA will be published soon which will provide more information on the Dual Core setup.

That should answer your questions. Thank you for your patience.

Regards,

Dheeraj