SPI for TDM codec

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StSi_2705941
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Hi guys,

I need use an audio codec type MC145481 where the SS signal is used as frame sync. I would load the SPI buffer with 16 byte and start the SPI that transfer all packet.

The codec require a frame sync on each word

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instead the SPI send a SS signal on each packet

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Can you suggest a solution for this behaviour ?

Thank you

BR

Stefano

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1 Solution

This definitely doable with the PSoC 5LP UDBs.

If you want to avoid modifying the Verilog implementation of the SPI, you can use a PWM to generate the SS line. The PWM should reset based on the SPI SS (on falling edge) and configure the period to generate the pulse on every 8th cycle.

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9 Replies
SampathS_11
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250 sign-ins 250 solutions authored 5 questions asked

Hello Stefano,

Can you kindly let us know which PSoC family you are referring to?

Best regards,

Sampath Selvaraj

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Hi Sampath,

I'm using 5LP family with SPI master 2.50,

Regards

Stefano

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StSi_2705941
Level 1
Level 1

Hi, nobody provide an answer  ?

Thanks and regards

Stefano

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StSi_2705941
Level 1
Level 1

Hello Sampath,

the suggestion of use a SS with other firmware controlled pin is not useful; too fast the SPI and too CPU load; I'm using SPI and DMA for avoid CPU load.

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This definitely doable with the PSoC 5LP UDBs.

If you want to avoid modifying the Verilog implementation of the SPI, you can use a PWM to generate the SS line. The PWM should reset based on the SPI SS (on falling edge) and configure the period to generate the pulse on every 8th cycle.

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Hi Rodolfo, than you for suggestion. It is working with PWM where the input clock is the same of the SPI input clock. About UDB solution I haven't experience.

About Verilog: can I modify the verilog implementation of the sttandard SPI ?

Is there a tutorial that explain how ?

Thank You

regards Stefano

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Great !!!, Many thanks for your help.

best regards

Stefano

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