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Dear Cypress Experts,
I have several questions in the ASP PPB, please help have a check, thanks!
Question 1: Why can not program the PPB even when the PPBL Lock is 1
LONER_TESTS # sf probe 2:0
SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB
LONER_TESTS # sspi 2:0.0 32 9fffffff
00012018
#Read the PPBL Lock Bit
LONER_TESTS # sspi 2:0.0 16 A7
0001
LONER_TESTS # sspi 2:0.0 48 65800040
000000000001
#PPB Read (Still 0xFF)
LONER_TESTS # sspi 2:0.0 48 E2
0000000000FF
#WREN
LONER_TESTS # sspi 2:0.0 8 06
00
#PPB Program
LONER_TESTS # sspi 2:0.0 48 E300000000
000000000000
LONER_TESTS # sspi 2:0.0 48 65000000
000000000000
#PPB Read (Still 0xFF)
LONER_TESTS # sspi 2:0.0 48 E2
0000000000FF
LONER_TESTS #
Question 2: Why does the A6h seems not work?
#Read the PPBL Lock Bit
LONER_TESTS # sspi 2:0.0 16 A7
0001
#WREN
LONER_TESTS # sspi 2:0.0 8 06
00
#Clear the PPBL Lock Bit to 0
LONER_TESTS # sspi 2:0.0 16 A6
0000
LONER_TESTS # sspi 2:0.0 16 A7
0001
LONER_TESTS #
Question 3: How can I use the PPB to protect the lower 1M for this flash?
SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB
Solved! Go to Solution.
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Hi,
Please see my comments below.
#Program PPB bits for first sector
LONER_TESTS # sspi 2:0.0 48 E300000000
000000000000
As per my understanding the number 48 in the above command (sspi 2:0.0 48 E300000000) is the length of SPI transaction. PPB program command (PPBP) needs only 40 clock cycles 'Command (8bit, 8 clock cycles) + Address (32 bit, 32 clock cycles)'. So, I think you are sending an extra data byte after address in this operation. Can you change the length of PPBP operation to 40 and test again?
sspi 2:0:0 40 E300000000
Please let me know the test results.
Thanks and Regards,
Sudheesh
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Hi,
Please find my comments below.
1. You have to read status register and make sure that PPB program operation is finished and device is not busy before reading PPB bits. Can you please modify your operations as below and test again.
- Read PPB lock bit and make sure it is '1'.
- Read PPB bits for first sector.
- Send WREN command.
- Program PPB bits for first sector.
- Read status register (0x05) until WIP bit SR1[0] becomes 0.
- Read and verify PPB bits.
2. You have to send WREN command before the command A6 (PLBWR). Please modify your sequence as below and test again.
- Read PPB lock bit.
- Send WREN command.
- Write PPB lock bit using 0xA6 command.
- Read status register (0x05) until WIP bit SR1[0] becomes 0.
- Read and verify PPB lock bit.
3. To protect a memory range using PPB bits, you have to set PPB bits for all the sector to be protected to 0x00.
If the above modification does not solve your issue, please attach logic analyzer waveform for the above operations.
Thanks and Regards,
Sudheesh
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Thanks for your quick answer!
For the question 1, the result still not ok. Could you help double check if the commands follow right as your process proposed?
#Read PPBL Lock Bit
LONER_TESTS # sspi 2:0.0 16 A7
0001
#Read PPB bits for first sector.
LONER_TESTS # sspi 2:0.0 48 E2
0000000000FF
#WREN
LONER_TESTS # sspi 2:0.0 8 06
00
LONER_TESTS # sspi 2:0.0 16 05
0002
#Program PPB bits for first sector
LONER_TESTS # sspi 2:0.0 48 E300000000
000000000000
#Read status register (0x05) until WIP bit SR1[0] becomes 0. ( Can not become to 0 )
LONER_TESTS # sspi 2:0.0 16 05
0002
LONER_TESTS # sspi 2:0.0 16 05
0002
LONER_TESTS # sspi 2:0.0 16 05
0002
LONER_TESTS #
#Read and verify PPB bits.
LONER_TESTS # sspi 2:0.0 48 E2
0000000000FF
LONER_TESTS #
For the question 2, the PPBL can be locked now.
LONER_TESTS # sspi 2:0.0 16 A7
0001
LONER_TESTS # sspi 2:0.0 8 06
00
LONER_TESTS # sspi 2:0.0 16 05
0002
LONER_TESTS # sspi 2:0.0 8 A6
00
LONER_TESTS # sspi 2:0.0 16 05
0000
LONER_TESTS # sspi 2:0.0 16 A7
0000
LONER_TESTS #
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Hi,
Please see my comments below.
#Program PPB bits for first sector
LONER_TESTS # sspi 2:0.0 48 E300000000
000000000000
As per my understanding the number 48 in the above command (sspi 2:0.0 48 E300000000) is the length of SPI transaction. PPB program command (PPBP) needs only 40 clock cycles 'Command (8bit, 8 clock cycles) + Address (32 bit, 32 clock cycles)'. So, I think you are sending an extra data byte after address in this operation. Can you change the length of PPBP operation to 40 and test again?
sspi 2:0:0 40 E300000000
Please let me know the test results.
Thanks and Regards,
Sudheesh
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Hi,
Great thanks, it works.
SOCFPGA_STRATIX10_ASOD # sspi 2:0.0 8 06
00
SOCFPGA_STRATIX10_ASOD # sspi 2:0.0 16 05
0002
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 40 E300000000
0000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0.0 16 05
0000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E200000000
000000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E200000001
000000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E2000000ff
000000000000
SOCFPGA_STRATIX10_ASOD #
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E20000ffff
000000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E20001ffff
0000000000FF
SOCFPGA_STRATIX10_ASOD #
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E20001ffff
0000000000FF
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 8 06
00
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 16 05
0002
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 40 E300010000
0000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 16 05
0000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E20001ffff
000000000000
SOCFPGA_STRATIX10_ASOD # sspi 2:0:0 48 E20002ffff
0000000000FF
SOCFPGA_STRATIX10_ASOD #
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Hi,
Thank you for the update. I am happy to hear that your issue has been resolved.
Thanks and Regards,
Sudheesh