DeMA,
Usually to make a 16-bit bus one has to use two Control Registers, 8-bit wide each, and combine their outputs into a single 16-bit bus. Then in C code, the MSB of the 16-bit value is assigned to one CReg (bits 8-15), and LSB to another CReg (bits 0-7). Note that such operation is not atomic, but sufficient in most cases.
To simplify this, I created custom ControlReg32 component, which has bus width up to 32-bit. You can find demo project here:
[Verilog] Register access using CY_SET_REG
In the basic dialog set the CReg width property to 16. Then in mein code use API:
CReg_Write(value);
/odissey1
DeMA,
Usually to make a 16-bit bus one has to use two Control Registers, 8-bit wide each, and combine their outputs into a single 16-bit bus. Then in C code, the MSB of the 16-bit value is assigned to one CReg (bits 8-15), and LSB to another CReg (bits 0-7). Note that such operation is not atomic, but sufficient in most cases.
To simplify this, I created custom ControlReg32 component, which has bus width up to 32-bit. You can find demo project here:
[Verilog] Register access using CY_SET_REG
In the basic dialog set the CReg width property to 16. Then in mein code use API:
CReg_Write(value);
/odissey1
