How to disable HOLD# function on SPI Flash

[CrTh_4535221]

We have run into issues in the past when accessing the devices using 1-1-4 based reads and writes.  Cypress has a pullup on IO3 that is used to disable the HOLD# feature when in x1 mode but how strong is this pullup?

Our controller leaves IO2 and IO3 tristate when driving the command and address so if the previous read or write drives IO3 low, it depends on the pullup to reach an active high state.

Is there an alternate way to disable this feature?

[DheerajK_81]

Please attach the datasheet of the memory chip you are interfacing with. Based on this we will be able to answer your questions further.

Regards,
Dheeraj

[CrTh_4535221]

S25FL512S attached.

[Apurva_S]

Hi Craig,

Thank you for contacting Cypress Semiconductor.

Could you please let me know what was the issue that you are facing? According to the datasheet, when quad mode is enabled, WP# becomes I/O2 and HOLD# becomes I/O3. The WP# and HOLD# inputs are not monitored for their normal functions and are internally set to high (inactive). Hence, when quad mode is enabled and even when you are sending the command/address over single SPI, HOLD# feature is disabled and it should not cause any problems.

Regards,

Apurva

[CrTh_4535221]

Apurva,

The issue that we are facing is not going into quad mode but working in x1 command, address and dummy bytes plus quad data (ie 1-1-4) mode.

So imaging reading N bytes of data that have content of 0. At the end of the read all 4 I/O lines are 0 (last nibble is 0). Then we want to send a second read using the 1-1-4 protocol. I/O0 is driven again for command, address and dummy but I/O3v might still be 0 because it is depending on the part’s internal pullup to raise it to a logic 1 else the part goes into HOLD# mode.

My question was what range of resistance does the internal pullup have.

Thanks,

Craig

[Apurva_S]

Hi Craig,

Thank you for your reply.

As mentioned by you, you are using 1-1-4 mode for reading the data. 1-1-4 means you must be using either the QOR command (0x6B) or the 4QOR command (0x6C). If you go to page 21 of the datasheet (https://www.cypress.com/file/177971/download ) you will find the following statement "The Quad Page Program and Quad Output Read commands send address to the memory only on I/O0. The other I/O signals are ignored because the device must be in Quad mode for these commands thus the Hold and Write Protect features are not active." This means, when quad mode has been enabled by setting the CR1[1] bit the hold feature is no longer available. Hence, if you are operating the device in quad mode you need not worry about the device going into hold state.

As per my understanding from your previous replies, you are able to read correct data in single SPI (1-1-1 mode) but are unable to read data in quad output read (1-1-4 mode). Please correct me if I'm wrong. I would like to ask you a few questions -

1. To operate the device in quad mode, you need to first set the quad bit in the configuration register 1 (CR1[1]). Have you set the quad bit? You can use the WRR command (0x01) to program configuration register bits. Please be careful not to program any of the OTP bits in the SR and CR.
2. Quad read commands require dummy cycles after sending the command and address and before the flash starts shifting the data out. The value of the required number of dummy cycles depending on the command is mentioned in Table 20 of the datasheet on page 50. Are you sending the correct number of dummy cycles required?
3. What do you mean when you say "The issue that we  are facing is not going into quad mode"? What kind of output are you observing? Is the output data corrupted or shifted by some bytes?
4. Do you have any SPI waveforms captured?

Best Regards,

Apurva

[CrTh_4535221]

Apurva,

While I agree that the HOLD# and WP# functions are disabled when QUAD mode(CR1[1] bit) is enabled. Does the 6B commands actually continute to operate in 1-1-4 mode when this bit is enabled? If so, it is different from the Micron and Macronix compatible parts. While I would welcome this feature, I don’t believe that it works this way. Can you confirm one way or the other?

I am still asking what the value range of the following pullups are:

Since the end customer purchases ~400K parts per month from multiple vendors for just this product line it would be good to know the complete range.

Thanks,

Craig

[Apurva_S]

Hi Craig,

Could you please provide us the part numbers or datasheet of the Micron and Macronix parts that you are referring to?

Regards,

Apurva

[CrTh_4535221]

Apurva,

Here is the part being used.

So it sounds like setting CR1[1] once will put the device in QUAD mode which disables the WP# and HOLD# functions and CMD 6B will still operate as a 1-1-4 cycle.

Please confirm.

Thanks for the help.

Craig

[Apurva_S · Accepted solution]

Hi Craig,

>> Here is the part being used.

     - Please mention the part number or datasheet of the Micron and Macronix parts that you referred to in your previous reply. The attached datasheet is of the Cypress part.

>> So it sounds like setting CR1[1] once will put the device in QUAD mode which disables the WP# and HOLD# functions and CMD 6B will still operate as a 1-1-4 cycle. Please confirm.

     - I would like to inform you that the quad bit of the configuration register 1 (CR1[1]) is a non volatile bit. Which means, once the quad bit is set it shall remain set till the time the programmer resets it by writing zero to that bit. The quad commands will work only when the quad bit is set, quad commands will not work when the quad bit is reset. The HOLD# function will be disabled throughout the time the quad bit is set (even when single SPI line is being used in 1-1-4 commands). The single SPI commands work under both conditions (both when CR1[1] is set and reset). The 6Bh command is the Quad Output Read (QOR) command, it expects the command, address and dummy cycles on a single line and provides the data on four lines. This command will only work when CR1[1] is set, and will not work when CR1[1] is reset. If the quad bit is set, the HOLD# function will be disabled through out the operation.

Hope this clears your confusion. If not, please feel free to ask your queries.

Best Regards,

Apurva

[CrTh_4535221]

Apurva,

Thank you for your assistance.

Craig