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Hi,
I made a board using a WM-AN-BM-23 WiFi module from USI. I cannot flash it (with JLink and Wiced).
I've bought an evalboard USI WM-AN-BM-23 in order to check if the problem is coming from my board or my setup.
Until now, I haven't manage to program my devboard (neither by embedded JTAG nor external J-Link).
Could someone can explain me how to flash a simple example (scan) to know if my board is flashable and working.
Here are more information about my setup: I'm on Windows 7 Pro 64-bit. I'm using Wiced V6.4 SDK. I updated the J-Link driver to libusbK (v3.0.7.0) with Zadig. I got the platform files from USI (BCMUSI23).
Here is the log I'm getting in openocg_log.txt
Open On-Chip Debugger 0.10.0+dev-00227-g0d15c62 (2018-03-27-15:19)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
trst_and_srst separate srst_nogate trst_push_pull srst_push_pull connect_assert_srst
trst_and_srst separate srst_nogate trst_push_pull srst_push_pull connect_assert_srst
adapter speed: 100 kHz
adapter_nsrst_delay: 100
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
jtag_ntrst_delay: 100
post_init_psoc6_setup
Info : J-Link V10 compiled Jul 10 2019 16:31:42
Info : Hardware version: 10.10
Info : VTarget = 3.354 V
Info : clock speed 100 kHz
Info : JTAG tap: BCM43909.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : BCM43909.cpu: hardware has 4 breakpoints, 4 watchpoints
force hard breakpoints
Info : JTAG tap: BCM43909.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Error: Error BCM43909.cpu: Reset was not successfully asserted
in procedure 'sflash_write_file'
in procedure 'sflash_init' called at file "apps/waf/sflash_write/sflash_write.tcl", line 261
in procedure 'post_init_43909_setup' called at file "apps/waf/sflash_write/sflash_write.tcl", line 160
in procedure 'reset' called at file "apps/waf/sflash_write/sflash_write.tcl", line 569
in procedure 'ocd_bouncer'
Thanks for your help,
Nicolas.
Solved! Go to Solution.
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Wifi+Bluetooth
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Dear Nicolas,
It seems to be hardware connection issue. Kindly check your schematics and soldering etc (most likely the TDO is always pulled high and hence the error)
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Dear Nicolas,
Could you please confirm whether you see the same issue in USI eval kit (USI WM-AN-BM-23) or the issue is only seen in your eval kit only?
For your eval kit, I would recommend switching back to J-Link driver and then try issuing reset command from JLinkCommander terminal and see if that is successful? ( If this step is successful, you can also try reading some memory locations and check)
From the mentioned log, it appears to be a hardware connection issue. Kindly double check that and give it a shot again. I am mentioning some relevant articles here
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Hello Raktim,
I see the issue on the evalboard. I want first to have a working setup using the evalboard before moving to my board.
I switched to original J-Link driver and it connects through JLink.exe:
SEGGER J-Link Commander V6.44e (Compiled Apr 5 2019 16:17:35)
DLL version V6.44e, compiled Apr 5 2019 16:15:03
Connecting to J-Link via USB...O.K.
Firmware: J-Link V10 compiled Mar 27 2017 14:04:52
Hardware version: V10.10
S/N: 50115987
License(s): GDB
VTref=3.348V
Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: CYW43907
Type '?' for selection dialog
Device>
Please specify target interface:
J) JTAG (Default)
S) SWD
T) cJTAG
TIF>
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "CYW43907" selected.
Connecting to target via JTAG
TotalIRLen = 4, IRPrint = 0x01
JTAG chain detection found 1 devices:
#0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
Scanning AP map to find all available APs
AP[2]: Stopped AP scan as end of AP map has been reached
AP[0]: APB-AP (IDR: 0x44770002)
AP[1]: JTAG-AP (IDR: 0x24760010)
Iterating through AP map to find APB-AP to use
AP[0]: APB-AP found
ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID:04-008BBC14 Cortex-R4
Found Cortex-R4 r1p4
4 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.0
Data endian: little
Main ID register: 0x411FC144
I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
TCM Type register: 0x00010001
MPU Type register: 0x00000800
System control register:
Instruction endian: little
Level-1 instruction cache enabled
Level-1 data cache enabled
MPU enabled
Branch prediction enabled
Memory zones:
[0]: Default (Default access mode)
[1]: APB-AP (AP0) (DMA like acc. in AP0 addr. space)
Cortex-R4 identified.
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
ResetTarget() start
J-Link script: Reset
J-Link script: Core did not halt after reset. Halting core...
J-Link script: Done
ResetTarget() end
J-Link>
I think there is an issue with reset pin from what I see from reset command from log.
I checked my wirings and everythings seems OK. However, when I press the reset button of the evalboard, I have the following output:
J-Link>r
Reset delay: 0 ms
Reset type NORMAL: Toggle reset pin and halt CPU core.
ResetTarget() start
J-Link script: Reset
J-Link script: Done
ResetTarget() end
J-Link>
What else should I check? Also, what is the difference between TRST and RESET pins?
Thanks again for your support,
Nicolas.
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JoYi_1844281 any thoughts on this?
Nicolas,
I am not particularly familiar with the USI eval kit that you are using. It would be better if you check the schematic to understand the difference between RESET and TRST pin.
Usually, in CY counterparts (CYW943907AEVAL1F), the reset pin is not tied to the TRST pin; instead it performs a complete backplane reset. Through JTAG, you are basically resetting the entire core.
The next step would be to try reading a memory location from J-Link Commander terminal. Maybe, you can try the following command
mem 0x14000000 100 hex
If you are able to successfully read the memory location, you can try the steps mentioned in Downloading through Jlink Segger in WICED SDK 6.2 and future releases and let us know if you are facing any errors.
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Hi Raktim,
I did the mem command and some valid data (not 0x00 or 0xFF). Do you have the memory mapping of the CYW43907? Because I don't have it in the USI datasheet.
Thanks for the link, I'm now able to flash my evalboard with J-Link. I'm now confused because I don't understand why, in some Cypress tutorials, it is written to use libusbK driver. Here, it was working while indicating the absolute path to JLink.exe.
Now, I wanted to flash my ownboard based on WM-AN-BM-23 but I have the following error when I try to connect with JLink.exe:
Connecting to target via JTAG
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Could not measure total IR len. TDO is constant high.
Cannot connect to target.
Do you have an idea why I get this output on my board but not on the evalboard? Soldering issue?
Here is the connection of the JTAG and configuration pins, if you can spot something:
Thank you,
Nicolas.
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Dear Nicolas,
It seems to be hardware connection issue. Kindly check your schematics and soldering etc (most likely the TDO is always pulled high and hence the error)
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