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Hi All,
I have recently begun to resurrect my hardware motion controller project and I am getting stuck as to the best way to achieve a certain task.
I would like the functionality of the Pulse Converter component, but for a whole bus. I have tried implementing it in Verilog but I am running into a couple of issues with driving output pins and getting a runt pulse (probably my inexperience with Verilog).
Does anyone have any suggestions?
Cheers
Greg
Solved! Go to Solution.
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Greg,
This YouTube video may be helpful
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`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 10/15/2019 at 20:00
// Component: Pulse_Ext
module Pulse_Ext (
output reg [7:0] output_bus,
input clock,
input [7:0] input_bus,
input Trigger
);
parameter Duration = 10;
reg [7:0] count;
//`#start body` -- edit after this line, do not edit this line
always @(posedge clock) begin
if (Trigger) begin
output_bus <= input_bus;
count <= Duration;
end
else begin
if (count > 0) begin
count <= count - 1;
end
if (count == 0) begin
output_bus <= 0;
end
end
end
//`#end` -- edit above this line, do not edit this line
endmodule
This is the verilog for the component I have tried, It has 4 terminals, (input_bus, output_bus, clock and Trigger).
It seems to work, but I get a runt pulse every few times the component triggers.
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A little bit (or byte 😉 more information could help us:
Pulse conversion what to what? Pulse width to integer? to voltage??
What precision is required?
What is the pulse frequency?
What is the bus width?
Are you using a Cypress Kit (Which one?)
Bob
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Sorry, my bad, first time and all that...
I am basically looking for a hardware pulse extender (buffer?), it doesn't need to interact with software or count. It just needs to take a short pulse in on the trigger pin (100ns, from a previous component) and then make the output_bus take the value of the input_bus for some time (clock count?) After that time has elapsed, the output_bus should return to GND again.
Ideally I would like an 8-bit bus which I think is doable.
I am using the CY8CKIT-059.
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And why don't you use 8 pulse converters ?
Bob
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Yeah, That is definitely one of the conclusions I am coming to. I just wondered if it was solvable with fewer Macrocells. In the mean time I have a solution:
Use a single pulse extender (on the trigger input, and have that drive the input to a digital Mux. That will switch between the mux inputs for the duration of the pulse, defaulting to input 0. And Muxes can have 32-bit widths which makes it a good solution.
I shall upload an image of my current solution shortly.
Greg
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So this seems to be a nice and simple solution, with a bus width between 2 and 32.
If anyone is interested, and someone tells me how, I will upload it as a component. Its very straightforward though.
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Hi,
This may not be the point but, I'd modify
================
if (count > 0) begin
count <= count - 1;
end
if (count == 0) begin
output_bus <= 0;
end
================
to
================
if (count > 0) begin
output_bus <= output_bus ;
count <= count - 8'd1 ;
end else begin
output_bus <= 8'd0 ;
count <= 8'd0 ;
end
================
moto
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Greg,
Good that solution works for you, but this is not a pulse converter. It is merely switches bus off for a while on external trigger.
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Thats very true, it isnt a pulse extender . As you may be able to tell from the slightly disjoint thread, I am not sure exactly the 'right' way to implement this, or even it if it is needed in the final design.
The system that lets me get away with this in this scenario is that my specific input_bus is a signal that is constant for minimum 10us, whereas the pulse needs to be 1us or so. If my input bus was pulsed as well, then this setup would not work.
Thank you all for your suggestions, it has certainly been interesting to dive into hardware programming
Greg
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GrDu,
Do all your inputs (with the short pulse width) synchronized to be valid at a specific time? If so, you can use an n-input latch with the latching signal being one that 'clocks' the inputs to the output. A Status Register in "Sticky mode" would do the trick. In this case the outputs remain what the inputs were until the next clock edge.
The trick for you if this is useful, is finding the source of the latching/clocking edge.
Len
"Engineering is an Art. The Art of Compromise."