25FL064 CS# at powerup

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jest_4523646
Level 1
Level 1

Hi,

we did a little (big?) mistake in the conception around the serial flash:

on the last serie of cards (hundreds) we forgot to put a pullup resistor on the CS# (ChipSelect#) signal coming from an FPGA.

The Vcc of the Flash rises about 40 ms before the CS# rises, which is contrary to what the datasheet requires (they should rise together with CLK and Data In too)

pastedImage_0.png

Still the cards seem to work fine, but i wonder if there is a risk of corruption or anything alike?

Thanks for your help,

best regards,

Jeremy

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1 Solution
BushraH_91
Moderator
Moderator
Moderator
750 replies posted 50 likes received 250 solutions authored

Hello Jeremy,

Thank you for contacting Cypress Community Forum.

Yes, this violates POR timing requirements and does have potential risk. The POR timing violation may cause flash not able to be initialized correctly, thus may cause unpredictable behaviors.

Have a wonderful day

Regards,

Bushra

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2 Replies
BushraH_91
Moderator
Moderator
Moderator
750 replies posted 50 likes received 250 solutions authored

Hello Jeremy,

Thank you for contacting Cypress Community Forum.

Yes, this violates POR timing requirements and does have potential risk. The POR timing violation may cause flash not able to be initialized correctly, thus may cause unpredictable behaviors.

Have a wonderful day

Regards,

Bushra

Hi Bushrah,

Thanks so much for this quick answer!

Have a good day

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