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A user needed this so for drill I created this as a starting point for them.
Basically the requirement was to create, from two frequencies, two signals, a sum frequency
and a difference frequency.
The two DDS in the white box and LCD were used to generate test signals and LCD
for debug. Those can be eliminated in design to free up resources for using other stuff.
I did this in PSOC 5LP, it may fit in the lower end family, PSOC 4. Would have to try
that out.
Design could benefit from a little more coding, eg. eliminate a small dither in frequency
due to finite arithmetic used in DDS and counters.
Timebase Gate for counters is set at 100 mS, so resolution is 10 Hz..
Also if needed output waveforms could easily be Sinusoidal if needed by using the WaveDac
onchip component.
Regards, Dana.
Solved! Go to Solution.
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Dana,
There are four DDS24 units in the project. I noticed that in their settings, the DDS clock frequency is set to 25.6MHz, while actual BUS_CLK in the project is 24MHz. This will lead to incorrect output from the DDS component. It is recommended to put actual (measured) BUS_CLK frequency there for better accuracy, or at least a nominal 24MHz value.
Since the bus output from DDS is not required, it is possible to use DDS32 (UDB-based) component instead of DDS24 (PLD-based), which should improve clocking speed. Draft version (no datasheet) of the DDS32 component can be found here:
Re: DDS24: 24-bit DDS arbitrary frequency generator component
I am not sure if such project can fit PSoC4 with 4 UDB blocks. It is possible to fit one DDS24 or one DDS32 component into P4200.
Re: How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ?
A solution may be to use one DDS24 (PLD placement) and one DDS32 (UDB Datapath placement).
PSoC4M with 8 UDB blocks should fit the design.
For higher accuracy or faster response it is possible to use fractional frequency meter component
Re: HELP, with example of frequency measurement Error
Regards,
/odissey1
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Dana,
There are four DDS24 units in the project. I noticed that in their settings, the DDS clock frequency is set to 25.6MHz, while actual BUS_CLK in the project is 24MHz. This will lead to incorrect output from the DDS component. It is recommended to put actual (measured) BUS_CLK frequency there for better accuracy, or at least a nominal 24MHz value.
Since the bus output from DDS is not required, it is possible to use DDS32 (UDB-based) component instead of DDS24 (PLD-based), which should improve clocking speed. Draft version (no datasheet) of the DDS32 component can be found here:
Re: DDS24: 24-bit DDS arbitrary frequency generator component
I am not sure if such project can fit PSoC4 with 4 UDB blocks. It is possible to fit one DDS24 or one DDS32 component into P4200.
Re: How can I handle a PSoC 5 community library DDS24 on PSoC 4 BLE device ?
A solution may be to use one DDS24 (PLD placement) and one DDS32 (UDB Datapath placement).
PSoC4M with 8 UDB blocks should fit the design.
For higher accuracy or faster response it is possible to use fractional frequency meter component
Re: HELP, with example of frequency measurement Error
Regards,
/odissey1
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Thanks for catching that freq error setting on DDS.
Regards, Dana.