There are four DDS24 units in the project. I noticed that in their settings, the DDS clock frequency is set to 25.6MHz, while actual BUS_CLK in the project is 24MHz. This will lead to incorrect output from the DDS component. It is recommended to put actual (measured) BUS_CLK frequency there for better accuracy, or at least a nominal 24MHz value.
Since the bus output from DDS is not required, it is possible to use DDS32 (UDB-based) component instead of DDS24 (PLD-based), which should improve clocking speed. Draft version (no datasheet) of the DDS32 component can be found here:
I am not sure if such project can fit PSoC4 with 4 UDB blocks. It is possible to fit one DDS24 or one DDS32 component into P4200.
A solution may be to use one DDS24 (PLD placement) and one DDS32 (UDB Datapath placement).
PSoC4M with 8 UDB blocks should fit the design.
For higher accuracy or faster response it is possible to use fractional frequency meter component
Thanks for catching that freq error setting on DDS.