- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Everyone,
I've been working with an FX3 to transfer data from an image sensor to a PC via an FX3. I've been using the 'SuperSpeed Device Design By Example' book by John Hyde and have implemented 'Slave FIFO Decribing' described in Chapter 11. This is the design where you use the DMA_Ready and DMA_Watermark flags to control data flow. Everything works as expected and I am receiving all data successfully from the FX3. However, I have notcied that the DMA_Watermark flag remains high for longer that expected which is slowing the data transfer. The first few buffer switches take around 0.5us, which is acceptable. However, after a few switches this gap suddenly becomes 6us. As it takes 40us to fill the buffer, it's pasuing for around 13% of the time. Also, if I double the buffer size (From 16K to 32K) we double the length of the pauses (to 12us).
Earlier in the book (chapter 9) it describes a 'Hardware Thread' model which is supposed to avoid those gaps. When I implement these, I find that the time to switch from thread0 to thread1 is 0, but switching back is 12us. It also says that 'larger gaps are caused by USB transfers not being able to keep up with the data rate'. Am I seeing a limitation of my PC here? Or is there something I am missing?
Thanks in advance
Chris
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Chris,
After the DMA watermark flag is asserted while writing to say, buffer0 of thread0, you will stop writing to buffer0 after certain number of 32-bit words (as per the water mark calculation). Now you start writing to buffer1 by monitoring the DMA ready flag of thread0 and not the watermark flag. So, watermark flag is used to end the transfer and the ready flag is used to start a transfer.
I think you are waiting for the watermark flag to get deasserted before another transfer. If I am wrong, please correct.
Regards,
Hemanth
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Chris,
After the DMA watermark flag is asserted while writing to say, buffer0 of thread0, you will stop writing to buffer0 after certain number of 32-bit words (as per the water mark calculation). Now you start writing to buffer1 by monitoring the DMA ready flag of thread0 and not the watermark flag. So, watermark flag is used to end the transfer and the ready flag is used to start a transfer.
I think you are waiting for the watermark flag to get deasserted before another transfer. If I am wrong, please correct.
Regards,
Hemanth
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Hemanth,
Thanks for your suggestion. I haven't had a chance to investigate yet as I have been working on other parts of the design. I should be able to look into it in the coming weeks.
Thanks
Chris