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Hello,
I've downloaded the schematic of CYBLE-416045-EVAL.
I can see that almost all signals between PSoC5LP and PSoC6 are straight connected.
However PSoC 6 Supply Voltage is 3.3 V max while PSoC5 LP VDDIO is 5 V derived from USB Bus.
From PSoC 6 Datasheet I can see that Max Input Voltage for any GPIO (Including OVT Inpius) is 3.6 V.
So: is it correct to feed PSoC 6 Input Pins straight with 5 Volts Outputs of PSoC 5 LP?
Thanks,
Alfonso
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Hello Alfonso,
Apologize for the delayed response. From the schematic, PSoC5LP(Kitprog2) GPIO pin P0[0] will have a voltage of P5LP_SIO_VREF from P6_VDD as shown in attached image. So all the GPIO Port P12 pins of PSoC5LP will have a maximum output voltage of P6_VDD.
Thanks,
P Yugandhar.
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Hello,
Can anybody please answer my question?
Thanks,
Alfonso
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Hello Alfonso,
PSoC 6 MCU family supports an operating voltage range of 1.7 V to 3.6 V. In PSoC 63 BLE Family Datasheet it was mentioned that the Max Input Voltage for any GPIO is 3.6V and Min voltage is 1.7V( for a supply voltage of 1.71 V to 3.6V). So, PSoC6 input pins cannot be connected with 5V. PSoC6 GPIO pins, including OVT pins, may not be pulled up higher than 3.6 V.
Thanks,
P Yugandhar.
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Hi Yugandhar,
I agree with you.
Please look at the schematic of the CYBLE-416045-EVAL.
KitProg2 VDDIO is 5 Volts (straight derived from USB Voltage).
Some KitProg2 signals are straight connected to PSoC6!!!
If I'm not wrong, Max GPIO Input Voltage Constraint is violated in Your EV Kit.
Alfonso
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Hello Alfonso,
Apologize for the delayed response. From the schematic, PSoC5LP(Kitprog2) GPIO pin P0[0] will have a voltage of P5LP_SIO_VREF from P6_VDD as shown in attached image. So all the GPIO Port P12 pins of PSoC5LP will have a maximum output voltage of P6_VDD.
Thanks,
P Yugandhar.