A question on Schematic of CYBLE-416045-EVAL

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
ALDE_1053476
Level 3
Level 3
10 replies posted 10 questions asked 10 sign-ins

Hello,

I've downloaded the schematic of CYBLE-416045-EVAL.

I can see that almost all signals between PSoC5LP and PSoC6 are straight connected.

However PSoC 6 Supply Voltage is 3.3 V max while PSoC5 LP VDDIO is 5 V derived from USB Bus.

From PSoC 6 Datasheet I can see that Max Input Voltage for any GPIO (Including OVT Inpius) is 3.6 V.

So: is it correct to feed PSoC 6 Input Pins straight with 5 Volts Outputs of PSoC 5 LP?

Thanks,

Alfonso

0 Likes
1 Solution
lock attach
Attachments are accessible only for community members.

Hello Alfonso,

Apologize for the delayed response. From the schematic, PSoC5LP(Kitprog2) GPIO pin P0[0] will have a voltage of P5LP_SIO_VREF from P6_VDD as shown in attached image. So all the GPIO Port P12 pins of PSoC5LP will have a maximum output voltage of P6_VDD.

Thanks,

P Yugandhar.

View solution in original post

0 Likes
4 Replies
ALDE_1053476
Level 3
Level 3
10 replies posted 10 questions asked 10 sign-ins

Hello,

Can anybody please answer my question?

Thanks,

Alfonso

0 Likes
Yugandhar
Moderator
Moderator
Moderator
500 solutions authored 1000 replies posted 5 likes given

Hello Alfonso,

PSoC 6 MCU family supports an operating voltage range of 1.7 V to 3.6 V. In PSoC 63 BLE Family Datasheet it was mentioned that the Max Input Voltage for any GPIO is 3.6V and Min voltage is 1.7V( for a supply voltage of 1.71 V to 3.6V). So, PSoC6 input pins cannot be connected with 5V. PSoC6 GPIO pins, including OVT pins, may not be pulled up higher than 3.6 V.

Thanks,

P Yugandhar.

0 Likes

Hi Yugandhar,

I agree with you.

Please look at the schematic of the CYBLE-416045-EVAL.

KitProg2 VDDIO is 5 Volts (straight derived from USB Voltage).

Some KitProg2 signals are straight connected to PSoC6!!!

If I'm not wrong, Max GPIO Input Voltage Constraint is violated in Your EV Kit.

Alfonso

0 Likes
lock attach
Attachments are accessible only for community members.

Hello Alfonso,

Apologize for the delayed response. From the schematic, PSoC5LP(Kitprog2) GPIO pin P0[0] will have a voltage of P5LP_SIO_VREF from P6_VDD as shown in attached image. So all the GPIO Port P12 pins of PSoC5LP will have a maximum output voltage of P6_VDD.

Thanks,

P Yugandhar.

0 Likes