s25fs512s not able to erase/write address location 0x00000 to 0x07FFF

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prTG_4469956
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Hi Team,

we are using s25fs512s in qspi mode with linux 4.14 kernel version, when we write first time to s25fs512s flash using sf write/dd command to write 0x0000 to 0x07FFF location the data will be written one time and we are not able to erase/write again but reset of the memory location we are able to erase/write.@

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Apurva_S
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100 likes received 500 replies posted 250 solutions authored

Hi Pradeep,

Thank you for contacting Cypress Semiconductor.

We have a patch for using FS-S devices with linux kernel 4.14. Are you using it in your code? If not, you can download it from here - https://www.cypress.com/documentation/software-and-drivers/cypress-spi-flash-drivers-linux-kernel-41...

Best Regards,

Apurva

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Hi Apurva,

Thank you for your reply, can i get dtsi example for s25fs512s flash for

latest driver and any logs to show how it probed in kernel and erased, and

need flash_erase source code which you have used

On Thu, Sep 19, 2019 at 12:31 PM ApurvaS_36 <community-manager@cypress.com>

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HI Apurva,

we are able to compile to driver , we need support on invoking the driver

by DTSI below is the DTSI snippet we are using please check and confirm is

it proper

&qspi

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Hi Pradeep,

I cannot see any snippet with your response. Could you please attach it again?

Regards,

Apurva

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Hi Apurva,

PFA

On Fri, Sep 27, 2019 at 12:12 PM ApurvaS_36 <community-manager@cypress.com>

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Hi Pradeep,

I have not received your attachment. Instead of replying to the email, could you please login to your account on the Cypress website and reply on the forum thread? Email attachments do not get posted as attachments in forum.

While posting your reply in the forum you will get an advanced editor option on the top right corner of the message box. You can attach files in the advanced editor.

Please feel free to ask if you any confusion.

Best Regards,

Apurva

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prTG_4469956
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HI Apurva,

Please find the attachment.

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Hi Pradeep,

FS-S devices have overlays of small 4kB sectors, be default mapped in at the bottom, i.e. bottom boot. These special sectors need special erase commands. Please go through the following KBA - S25FS-S Support Under Linux - KBA218975

Please let me know if you have any further queries.

Best Regards,

Apurva

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Hi Apurva,

Can you please let me know the command list and i have got driver from you

which is not working in linux 4.14 version

On Fri, Sep 27, 2019 at 3:05 PM ApurvaS_36 <community-manager@cypress.com>

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Hi Pradeep,

Could you please let me know the processor that you are using?

Regards,

Apurva

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HI Apurva,

We are using LS2088A from NXP.

On Fri, Sep 27, 2019 at 4:52 PM ApurvaS_36 <community-manager@cypress.com>

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Hi Pradeep,

Please apply the two patches attached. Once the patches are applied, the quadspi driver can be selected in the kernel configuration menu under (Device Drivers > Memory Technology Support > Cypress SPI Device Support)

Best Regards,

Apurva

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HI Apurva,

Yes we have compiled using and able to generate object files also and we

are facing issue for inovking the driver from DTSI.

On Tue, Oct 1, 2019 at 11:20 AM ApurvaS_36 <community-manager@cypress.com>

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Hi Pradeep,

Could you please share DTSI, DTS and error message or bootup log?

Attached is what works for imx8mq-evk board.

  1. Your partition may be wrong. So please note the changes to the partition.
  2. Compatible controller in dtsi should be “fsl,ls2088a-qspi”
  3. For Quad IO Mode, following needs to be enabled (uncommented) in dts file.

           // cy-snor,quad-read;

           // cy-snor,quad-write;

Best Regards,

Apurva

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Hi Apurva,

We have tried DTSi modifying for cypress still we are facing issue can you please provide me below details based on cypress note

Note
99. FS512S devices are user configurable to have either a hybrid sector architecture (with eight 4-KB sectors / one 224-KB sector and all remaining sectors are uniform
256 KB) or a uniform sector architecture with all sectors uniform 256 KB. FS-S devices are also user configurable to have the 4-KB parameter sectors at the top of
memory address space. The CFI geometry information of the above table is relevant only to the initial delivery state. All devices are initially shipped from Cypress with
the hybrid sector architecture with the 4-KB sectors located at the bottom of the array address map. However, the device configuration TBPARM bit CR1NV[2] may be
programed to invert the sector map to place the 4-KB sectors at the top of the array address map. The 20h_NV bit (CR3NV[3} may be programmed to remove the 4-KB
sectors from the address map. The flash device driver software must examine the TBPARM and 20h_NV bits to determine if the sector map was inverted or hybrid
sectors removed at a later time. How to set the sector at bottom.

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Hi Pradeep,

This note talks about configuring hybrid sector architecture in S25FS512S device.

  • As described in the note, the CR3NV[3] bit of Configuration Register 3 determines whether hybrid sector architecture will be enabled or not. If the bit is 1 it means hybrid sector architecture is disabled, where as when the bit is 0 it means hybrid sector architecture is enabled. The default state of this bit is 0 which means hybrid sector architecture is enabled.
  • And, bit CR1NV[2] determines the location of the parameter sectors. When this bit is 1 the parameter sectors are aligned at top (high address), where as when this bit is 0 the parameter sectors will be aligned at the bottom (low address). The default state of this bit is 0 which means parameter sectors are aligned at the bottom.

Therefore, by default when shipped from Cypress, the parts will have the parameter sectors enabled and aligned at the bottom.

Regards,

Apurva

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