AN4065

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GaTa_430276
Level 1
Level 1

Hello,

I have a question with regarding to the AN4065.  On page 24, it stated that “The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.”  What does 1024 cycle refers to?  Is it, READ CYCLE, WRITE CYCLE or CLOCK CYCLE?  Thank you!

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PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

The 1024 or 2048 cycles for QDR II+ refers to the clock cycles. If the clock input provided to the device is as per the datasheet specification then the PLL present inside the device will take 1024 cycles to lock itself and the Output Impedance circuitry will adjust the output impedance of the device as per the resistance connected to the ZQ pin.

Thanks,

Pradipta.

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PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

The 1024 or 2048 cycles for QDR II+ refers to the clock cycles. If the clock input provided to the device is as per the datasheet specification then the PLL present inside the device will take 1024 cycles to lock itself and the Output Impedance circuitry will adjust the output impedance of the device as per the resistance connected to the ZQ pin.

Thanks,

Pradipta.

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Thank you for responding to my question.  How does the READ and WRITE cycle impact the calibration?  My observation, is that when I did a large block of READ it got error as the it got deeper into the memory address.  The device behaved as it went out of calibration.  But when I performed some WRITE in between the READ I no longer detected error.

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Hi Garrett,

This is not the expected behavior. The number of read cycles should not induce errors or remove them. We will need to debug the issue for eliminating the errors. Can you provide us with the scope shots for the read (both pass and fail) and the schematics for the memory side.

Thanks,

Pradipta.

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