Port pins are not changing synchronously

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NiVa_4337911
Level 3
Level 3
First like received

Hi,

I am trying to write data to a port and then using a latch signal. But some of the port bits are changing later than the latch signal as shown in the picture below:

IMG_4542.JPG

The first four from the bottom are address and the last one is the latch (WR_N). The problem here is: the latch closed before loading the data.

void MUXSetAddress(uint8_t address)

    MUX_Addr_Write(address & 0x0F);

    MUX_EN_Write(1);

    CyDelayUs(1); 

    // Enable write

    MUX_WR_N_Write(0);

    CyDelayUs(1);

    MUX_WR_N_Write(1);

    MUX_EN_Write(0);

}

All are from same port, where the address is p[3:0].

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1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

When you are using a CY8CKIT-059 the pin P3_2 has a 1µF bypass cap attached. This might cause a delay

Bob

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3 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

When you are using a CY8CKIT-059 the pin P3_2 has a 1µF bypass cap attached. This might cause a delay

Bob

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Thank you, I didn't notice those caps.

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

NiVa,

If Bob's answer does not answer your issue, please share your project with the community.

In general, any logic clocked off of the same clock will change within a few 10's of nanoseconds from the other outputs.  the exception as Bob posted is when there is different output external loading.

Len

Len
"Engineering is an Art. The Art of Compromise."
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