Asynch Path Warning with SRFF

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alfi_297226
Level 1
Level 1
5 questions asked Welcome! 5 replies posted

I get  an Asynch Path Warning that I don't understand and can't isolate further. It is caused by adding the standard SR Flip-flop component to a circuit in a PSoC 5LP design.

Attached is an archive bundle of a debug workspace called "Asynch Debug" which contains two simple projects one with the SRFF component added downstream of a Counter component and one without the SRFF. The project with SRFF throws the Static Timing Warning and the one without it does not.

Why does this happen?

Thank You

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Bob_Marlowe
Level 10
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You need a sync component as Iinserted in your projects.

Happy coding

Bob

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Bob_Marlowe
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You need a sync component as Iinserted in your projects.

Happy coding

Bob

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Ekta_N
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello

You need to add sync component as suggested by Bob between the Counter_1 and the d-flip flop. In general you should add Sync Components to fixed function block outputs  that are routed to UDB-based Components/Clocks.

For more details on this, please refer to the page 23 of PSoC® 3, PSoC 4, and PSoC 5LP Digital Design Best Practices Appnote.

https://www.cypress.com/file/179061/download

Best Regards

Ekta

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