CY4541 Evaluation Kit: The output BaudRate of the SW Tx Uart not correct

[coch_1069476]

In the CYPD4225-40LQXI_notebook project, after I  add a ''SW Tx Uart" component and use it in baudrate 115200. I measured the waveform and found the output baudrate is 1.25x slower than 115200. What's happened? I don't change the system frequency and it's 48MHz.

[SaBh_294166]

Hi. Some ideas to check:

1) Is the UART IP the latest? The supplied project files for this kit have dated components so be sure that they are current.

To update the components:

Can I update my PSoC Component in the PSoC Creator?

2) Try the following UART project example and share your results:

PSoC UART Example - Microcontroller - eewiki

[coch_1069476]

1. I have update the "SW Uart Tx" componet to the newest version 1.5 before I ask the question.

2. The Hardware Uart is working normally in my project.

3. After I changed the code compiled method to released. I got the same issue.

4. After I create a new empty project, setting the SYSCLK to 48MHz and just add the "SW Uart Tx" component. There is the same issue. I think it's the "SW Uart Tx" component problem.

5. After I set the funtion CyDelayFreq(38752293) (org is 48000000). I got the correct baudrate. But I don't know why.

[YiZ_31 · Accepted solution]

Hi，

Try to moderate the CLK divider of HFCLK from 1 to 2. Then the Uart can work normally.

Regards,
Eddie

[coch_1069476]

@EddieZ_31

Thanks the solution and it's workable. But why can't I use 48MHz SYSCLK/HFCLK?