HyperBus Memory Controller IP does not response write transaction during write response(BVALID remains deasserted)

[user_4064026]

I implemented your HyperBus Memory Controller IP on several
technology. Now I am trying it on different technology. I have a issue and I
want to learn cause of problem. I configured the HyperBus Memory Controller IP
as compatible with HyperRAM over AXI register interface. There was not any
error for both read and write operation to IP registers. However IP does not
assert BVALID write response channel signal When I try to write to HyperRam
over AXI memory interface.Can you help me about this issue?.What could be cause
of this issue?

[TakahiroK_16]

Hello,

Could you make sure the following items?

1) AXIm_ACLK is supplied

2) If you are using AXI4, AXIm_WID is fixed to 0

Best Regards,

Takahiro

[user_4064026]

Hello,

I checked AXIm_ACLK and It is supplied. Also AXIm_ACLK and AXIr_CLK are same.There is not any problem AXI Control Register side.

I am using AXI4 and I checked AXIm_WID and It is fixed to 0.

Best Regards,

Emre

[SudheeshK]

Hello Emre,

Since apologies for the delay in our response.

1. Could you please let us know the hardware that you use (FPGA or Evaluation boards)?

2. Did you receive any example VIVADO projects from Cypress for Xilinx FPGA?

Thanks and Regards,

Sudheesh

[user_4064026 · Accepted solution]

Hello Sudheesh,

I solved the problem thanks for your responses.The problem was IP initialization during reset procedure.

Best Regards

Emre