Power up sequence using UDBs (timers/counters)

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COAL_3784046
Level 1
Level 1
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Hello everybody,

Im trying to do a basic power up sequence (using LP5) that combines both HW signals and SW signals and i cannot find a valid method for doing it using UDBs and digital logic.

Basically, on HW signal change (low to high) this timer/counter/etc shall start counting specific delay before activating a power circuitry enable pin. Later on, the same sequence shall work but in this case, the inputs are both HW and SW signals for enabling different circuitry peripheral.

I tried with both timers and counters, none of them seems to work.

Can your experience help me through this?

Appreciate your support.

BestRegards

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1 Solution

Can you share the project? You definitely need to write some lines of code to initialize the timers.

View solution in original post

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10 Replies
RodolfoGL
Employee
Employee
250 solutions authored 250 sign-ins 5 comments on KBA

There is a component called Voltage Sequencer that does exactly what you are looking for. It is implemented with a mix of hardware and firmware.

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Thanks RodolfoG_11.

I tried this one, but is not working in my case. Followed exactly as datasheet specifies. Anyway,

The problem with this one is that is using MCU for the sequence, and i need pure hardware (udb) to be independent of MCU during this sequence.

Do you think that are any other solutions?

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If that's the case, you will need to design this logic in Verilog or using high level hardware components. How may power rails you need to drive?

Ok, then i will search for Verilog lessons for a full refreshing. If you have something in mind, please share.

I need to control only 2 enables (with two different delays starting from initial trigger or sequentially one after another)

The problem is configuring the timers/counters to do this job, purely hardware without any mcu interaction.

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If it is only 2 enables, then you probably are OK using the high level hardware components. Use two timers, so you don't need to reconfigure them.

If you can provide a time diagram of all the signals involved, we can put something together for you.

Thanks RodolfoG_11,

It would be approximately like this diagram.

tempsnip.png

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OK. You can use two timers for this. One with 200 ms period (Timer A) and the other with 400 ms (Timer B).

The Timer A is triggered on rising edge of ON_Trigger.

The Timer B is triggered on TC of Timer A.

EN_LDO1 is asserted on TC of Timer A.

EN_BUCK is asserted on TC of Timer B.

You can also add some AND gates to the logic when ON_Trigger de-asserts, so your enable outputs also de-assert.

I tried using timers but somehow, it does not count... i explain my configuration (based on your solution).

Timer 8bit:

- Trigger - Rising edge of ON (input gpio signal after debouncer)

- Enable - Logic High.

- Clock - low clock in this case for testing (100Hz)

- Reset - Logic Low.

I tied out the TC to external GPIO output to confirm behavior, and its true, once the Trigger input detects Rising egde, the TC switch to High without counting. So, the timer acts exactly like a FlipFlop.

Any thoughts why this is happening? (no c++ line of code in MCU apart from CyPmAltAct(0,0), just testing the digital logic and avoid usage of MCU).

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Can you share the project? You definitely need to write some lines of code to initialize the timers.

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Thats it! I thought that by using UDBs components i avoid all MCU interference in the process.

Now i added these lines and worked like charm.

    Timer_1_Init();

    Timer_1_Start();

Appreciate your support RodolfoG_11

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