Sorry to say that are no example projects where FX2LP is interfaced to FPGA in GPIF mode and AN's explaining configuration on the FPGA side as a slave.
Please refer to AN63620 which uses GPIF to configure the FPGA. Once the FPGA is configured then the mode is switched to slave FIFO mode.
AN61345 implements interface between FX2LP and FPGA where FX2LP is in slave FIFO mode.
AN84868 uses FX3 to configure the Xilinx FPGA using GPIF II.
Thanks for the info.
So the usual use case that is documented is where the FPGA is the master?
Also, there are no use cases where GPIF is translated to AXI?
FX2LP is mostly used in slave FIFO mode where FPGA acts as a master.
Sorry to say that there are no examples where GPIF is translated to AXI.