How to use an asynch SRAM (CY62256N) like a synchronous part?

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StRh_4354941
Level 1
Level 1

I am building a homebrew CPU and have now reached the point of designing the SRAM part. I plan of using a simple 32K x 8bit static RAM (such as the Cyprus CY62256N). My concern is that the part is asynchronous but I want it to act like a synchronous part.

In the the rest of my design, registers are written to on the rising edge of the clock with the required new value already on the data lines.During the rest of the clock period the new instruction is processed and a new value might be placed on the data lines. This is fine because the register only updates on the rising edge and not later on, even though the clock happens to still be high.

I presume this approach will not work with asynchronous SRAM. I am concerned that the rising edge of the clock will update the SRAM, but if the clock happens to still be high when the value of the data lines is updated for the next instruction it will cause another update that is not wanted.

Is there some common technique to achieve what I need?

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SudheeshK
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250 sign-ins First question asked 750 replies posted

Hello Steve,

As you already know, CY62256N does not have a clock input and cannot be used as a synchronous device. To perform read and write operations to this asynchronous SRAM, you have to control the following signals CE#, WE#, OE#, Address and Data signals as described in our datasheet, https://www.cypress.com/file/43841/download. If you want to access our SRAM w.r.t clock, then you have to implement additional logic to to control above signals using clock signal. Please see switching waveform given in datasheet (page 😎 for more information.

Thanks and Regards,

Sudheesh

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SudheeshK
Moderator
Moderator
Moderator
250 sign-ins First question asked 750 replies posted

Hello Steve,

As you already know, CY62256N does not have a clock input and cannot be used as a synchronous device. To perform read and write operations to this asynchronous SRAM, you have to control the following signals CE#, WE#, OE#, Address and Data signals as described in our datasheet, https://www.cypress.com/file/43841/download. If you want to access our SRAM w.r.t clock, then you have to implement additional logic to to control above signals using clock signal. Please see switching waveform given in datasheet (page 😎 for more information.

Thanks and Regards,

Sudheesh

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