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Using CY8C29466 and the BootLdrI2C module. The PSoc is used as a slave addressed by a Linux SBC acting as Master.
When I try and read from a register in the PSoC, using a sub-address, (e.g. linux command i2cget -y 0 0x30 0) the PSoc interprets the read as a write; both read and write complete flags get set simultaneously.
Clk and Data signals look like this. (Resistance in series to slave ensure signals driven by slave don't go to 0V)
Any help/thoughts gratefully received.
Solved! Go to Solution.
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PSoC 1
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- psoc1 i2c
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Hello Peter,
Sorry for the delay.
Could you please check the code example "CE58027 I2CHW User Module Slave Operation" in the PSoC Designer by sending the Linux commands to the PSoC1 device. Please let me know if you see any issues.
Also, please check your project with the Bridge control panel by sending I2C commands(read/write) to the PSoC1 Device.
Thanks,
P Yugandhar.
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Can you kindly explain how you get both the Read and Write complete flags set?
Best regards,
Sampath Selvaraj
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Thank you for your reply. Attached is the file that deals with the i2c interface, the project archive is also attached. I2C_Poll is called from main. I print out the status register to a UART on the PSoC.
If I issue this command
i2cget -y 0 0x30 0
which is an I2C read, the UART sends out this data
read
1010101
write
1010101
Stop
Showing both read and write complete flags are set simultaneously, in addition to the read and write no_err flags.
Regards Peter
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This is because the I2C Master writes the sub-address first, causing a write complete status. Then it reads the slave, causing a read complete.
Best regards,
Sampath Selvaraj
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OK, thanks.
I have two issues.
1) As described above. If I perform a read from a sub-address both read and write flags are set and the code has no way of knowing which type of access has been performed. The bootloader sample code does not deal with this type of access, since it assumes only one type of access can happen at once. Do you have any sample code that deals with this? Perhaps there are API functions that I am unaware of.
2) If I perform a write to a sub-address (eg i2cset 0 0x56 0 1) no ack is sent at the end and so Linux replies with "i2cset: write failed: No such device or address" although the access has been completed on the PSoC.
Perhaps these two issues are really the same, namely reads/writes to sub-addresses are not supported. Any guidance welcomed.
Best regards
Peter
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An update. 2) above required the write buffer in the PSoC to be 1 larger than actual data transmitted. Then the ack comes back and Linux is happy. Still left with 1) though.
Best Regards
Peter
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Can you kindly reduce the poll interval? In that case you would be seeing the write complete earlier, and reset the write complete flag. And when the read transaction is complete, you will see only the read flag asserted.
Best regards,
Sampath Selvaraj
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Thanks for the suggestion, but I need the interface to respond to reads and writes and I won't know if the write is from a read or from a genuine write. Please let me know if I'm missing something.
Best Regards
Peter
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Hello Peter,
Sorry for the delay.
Could you please check the code example "CE58027 I2CHW User Module Slave Operation" in the PSoC Designer by sending the Linux commands to the PSoC1 device. Please let me know if you see any issues.
Also, please check your project with the Bridge control panel by sending I2C commands(read/write) to the PSoC1 Device.
Thanks,
P Yugandhar.