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how to configure SPIM_SCBCLK to 24MHZ?
can someone explain that on what parameter it depends on?
i have research documents from Cypress, i didn't find a proper flow of solution.
Thanks,
SD
Solved! Go to Solution.
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Hi,
I just made one for CY8CKIT-042.
Since I'm using only 1 SPI, I connected MOSI (P2[0]) and MISO (P2[1]) to test.
Schematic
SPIM Config (1)
SPIM Config(2)
Note: Although the default buffer size is 4, as I set num to send to 8, I made Buffer Size bigger (16).
Pin assignment
main.c
==================
#include "project.h"
#include "stdio.h"
char str[128] ; /* print buffer */
void print(char *str)
{
UART_UartPutString(str) ;
}
void init_hardware(void)
{
UART_Start() ;
SPIM_Start() ;
CyGlobalIntEnable; /* Enable global interrupts. */
}
void splash(void)
{
sprintf(str, "UDB SPI(Master) Loop Back Test (%s %s)\n", __DATE__, __TIME__) ;
print(str) ;
}
#define TIMEOUT_MS 1000
#define RX_BUF_LEN 32
#define RX_BUF_LEN 32
int main(void)
{
int offset = 0 ;
int i ;
uint8_t tx_buf[RX_BUF_LEN] ;
uint8_t rx_buf[RX_BUF_LEN] ;
int tx_count, rx_count ;
int num_to_send = 8 ;
int timeout_count = 1000 ;
init_hardware() ;
splash() ;
for(;;)
{
/* prepare data to send */
for (i = 0 ; i < num_to_send ; i++ ) {
tx_buf = offset + i ;
}
tx_count = num_to_send ;
/* send data */
SPIM_PutArray(tx_buf, tx_count) ;
/* wait for the data to be sent */
while(SPIM_GetTxBufferSize() > 0) {
timeout_count++ ;
if (timeout_count >= TIMEOUT_MS) {
print("SPIM Sending Timeout!\n") ;
break ;
}
CyDelay(1) ; /* wait 1ms */
}
/* receive data */
rx_count = 0 ;
while(SPIM_GetRxBufferSize() > 0) {
rx_buf[rx_count] = SPIM_ReadRxData() ;
rx_count++ ;
if (rx_count >= RX_BUF_LEN) { /* overflow! */
break ;
}
}
print("Data Sent : ") ;
for (i = 0 ; i < tx_count ; i++ ) {
sprintf(str, "%02X ", tx_buf) ;
print(str) ;
}
print("\n") ;
print("Data Received: ") ;
for (i = 0 ; i < rx_count ; i++ ) {
sprintf(str, "%02X ", rx_buf) ;
print(str) ;
}
print("\n\n") ;
CyDelay(2000) ; /* wait 2 sec */
offset++ ;
if (offset >= 20) {
offset = 0 ;
}
}
}
==================
Tera Term Log
moto
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The SPIM_SCBCLK is an internal clock defined and used by the SPIM component.
Its frequency is a product of the "Data rate" and the "Oversampling"
So, when the "Data rate" is set to 8Mbps and the "Oversampling" is set to 6, a 48MHz clock is desired by the SPIM component.
But it is unavailable to provide a 48MHz clock to the SPIM component because the IMO clock is set to 24MHz in this case.
Here the "Tolerance" parameter is effective. The Tolerance is set to -100% to +2% This means any clock frequency is acceptable lower than or equal to 102% of 48MHz. So, PSoC Creator selects 24MHz which is the highest clock frequency made from existing clocks.
Regards,
Noriaki
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Hello Noriaki,
That makes sense. Thanks for the quick response on this clock issue.
But in the case explained below, we expect the “SPIM:sclk_m” to drive at 24MHz.
But with this configuration of Data Rate = 8MBPS and Oversampling of 6, we are getting clock rate of 4MPBS as shown in below pic as Actual Data Rate I,e 4000 KBPS,
https://community.cypress.com/servlet/JiveServlet/downloadImage/2-203188-399616/GS004361.png
What are the other factors which affect the SPIM:sclk_m to drive low, like 4MPBS even though desired was 24MPBS?
Please give us some configuration, which drives SPIM:sclk_m with 24MHz.
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If you set the IMO frequency to 48MHz, you can use 8Mbps Data rate. This is the maximum SCLK frequency using the SCB.
If you want more fast SCLK, please consider to use the UDB version of "SPI Master" component.
The maximum data rate is 12Mbps a little bit faster.
Regards,
Noriaki
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Any sample code examples available for the UDB version of "SPI Master" component?
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Hi,
I just made one for CY8CKIT-042.
Since I'm using only 1 SPI, I connected MOSI (P2[0]) and MISO (P2[1]) to test.
Schematic
SPIM Config (1)
SPIM Config(2)
Note: Although the default buffer size is 4, as I set num to send to 8, I made Buffer Size bigger (16).
Pin assignment
main.c
==================
#include "project.h"
#include "stdio.h"
char str[128] ; /* print buffer */
void print(char *str)
{
UART_UartPutString(str) ;
}
void init_hardware(void)
{
UART_Start() ;
SPIM_Start() ;
CyGlobalIntEnable; /* Enable global interrupts. */
}
void splash(void)
{
sprintf(str, "UDB SPI(Master) Loop Back Test (%s %s)\n", __DATE__, __TIME__) ;
print(str) ;
}
#define TIMEOUT_MS 1000
#define RX_BUF_LEN 32
#define RX_BUF_LEN 32
int main(void)
{
int offset = 0 ;
int i ;
uint8_t tx_buf[RX_BUF_LEN] ;
uint8_t rx_buf[RX_BUF_LEN] ;
int tx_count, rx_count ;
int num_to_send = 8 ;
int timeout_count = 1000 ;
init_hardware() ;
splash() ;
for(;;)
{
/* prepare data to send */
for (i = 0 ; i < num_to_send ; i++ ) {
tx_buf = offset + i ;
}
tx_count = num_to_send ;
/* send data */
SPIM_PutArray(tx_buf, tx_count) ;
/* wait for the data to be sent */
while(SPIM_GetTxBufferSize() > 0) {
timeout_count++ ;
if (timeout_count >= TIMEOUT_MS) {
print("SPIM Sending Timeout!\n") ;
break ;
}
CyDelay(1) ; /* wait 1ms */
}
/* receive data */
rx_count = 0 ;
while(SPIM_GetRxBufferSize() > 0) {
rx_buf[rx_count] = SPIM_ReadRxData() ;
rx_count++ ;
if (rx_count >= RX_BUF_LEN) { /* overflow! */
break ;
}
}
print("Data Sent : ") ;
for (i = 0 ; i < tx_count ; i++ ) {
sprintf(str, "%02X ", tx_buf) ;
print(str) ;
}
print("\n") ;
print("Data Received: ") ;
for (i = 0 ; i < rx_count ; i++ ) {
sprintf(str, "%02X ", rx_buf) ;
print(str) ;
}
print("\n\n") ;
CyDelay(2000) ; /* wait 2 sec */
offset++ ;
if (offset >= 20) {
offset = 0 ;
}
}
}
==================
Tera Term Log
moto
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Hello Tanaka,
Thanks for the reply.
I could verify the loopback behavior and it's working fine.
But I am not getting any clock pulse on the pin-44 (P1.7) pin as configured for SCLK in this project.
Are we missing anything here?
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Hi,
Actually it was me who was missing something.
In CY8CKIT-042, pin-44 (P1[7]) is used for AREF and connected to a capacitor,
which means that this pin is not good for high frequency signal.
But as I was doing loop back, PSoC actually did not care much about the SCLK...
Anyway, I changed the SCLK to P2[2], which is next to MISO/MOSI
Now I can observe SCLK, although this oscilloscope is not quite fast enough...
I'm sorry for the inconvenience.
moto
P.S. I wonder how I could ended up using P1[7] for SCLK... orz
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Thanks. That worked.
Actually I had a doubt but couldn't get anything on UDB discerption.
And one more thing. From where we can get this UDB code examples? Because I can see only SCB code examples from my creator IDE!
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Hi,
> That worked.
I'm glad hearing that!
> And one more thing. From where we can get this UDB code examples?
IMHO, Cypress Developer Community (aka here) and KBA should be the best place to search.
But as you already know, we are not always lucky enough to find an expecting sample.
In such case, what I usually do is/are
(1) Read the component datasheet, which we can open the components' catalog.
I think that the component datasheet is the most complete and reliable information for the component.
Especially it matters when there is/are difference(s) between UDB component and SCB component.
(2) Having said that still I must admit that usually I refer to the generated source itself.
So for this case, SPIM.h and SPIM.c
SPIM.h, with the header we can see what kind of APIs are available.
Then I read the SPIM.c, I like the way Cypress Programmers comment their code.
They usually list choices of parameter (defined ones), which help me a lot to write code(s).
(3) And the last but not the least, they recently opened "Community Code Examples" area.
Not only there is/are examples, I think that you can request an example there.
Well, can we call it a day?
moto
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Hi,
Thanks for the Great help..!
Everything is working fine, but here we are just following Polling mechanism means, we are not expecting any data or response from Slave, so MISO pin is not required.
As per sample code which you referred, MISO is not required and it is configured to some GPIO. we want to use same GPIO for some other purpose.
i tried to delete the pin from top design but its throughout an error.
please help us, if anything is possible as per our requirement.
Deepthi
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Hi,
I tried following two cases, both could be compiled.
May be (1) uses less resource, I suppose.
(1) Connect logic '0'
(2) Loop back MOSI to MISO
moto
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Hi Tanaka,
Thanks for the reply.
In both the cases mentioned above, MISO pin will be configured but only the input varies.
But, is it possible to remove the MISO pin completely from the design so that we can use that pin for some other purpose instead of SPI data.
We require only 2 line CLK & MOSI for this SPI. IS it possible? If so, then how to remove this MISO form design?
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Hi,
> In both the cases mentioned above, MISO pin will be configured but only the input varies.
That is odd.
In my project, the pin list showed
Have you tried to Clean and Build?
Or at least "generate application" again?
moto
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Even in my project, I can see MISO is deleted in pin sections. But Getting below error.
Here is my Top design.
Errors getting:
I am suspecting that, below configuration from SPI block is throwing the error.
Is it possible to overcome this error?
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Hi,
I'm afraid that the "logic '0'" component is not connected to the miso pin,
it's only overlapping.
Could you move the "logic '0'" component to the left and connect it to the miso using wire?
moto
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After I connect Logic 0 correctly, Project built successfully but getting following errors.
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Hi,
Seeing your schematic, I'm still not quite sure if it's connected right.
Would you please try following?
(1) Delete the "logic '0'" component from the schematic
(2) Area select the left half of the SPIM component, so that if there is are wires left, they will be selected
(3) Then if there is/are remaining MISO related wire, delete them
(4) Place a new "logic '0'" component apart from the SPIM
(5) Use wire to connect "logic '0'" and MISO pin of SPIM
(6) Try "Clean and Build"
moto
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Yes Tanaka.
It's working fine now. Thanks.