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Hi All,
I want to collect data from 12 bit ADC and sent it to PC through CYUSB FX2LP usbcontroller with help of 7series FPGA XC7S15. In this application, I'll going to use FX2LP in slave FIFO mode (CYUSB as Slave). So all slave configuration is USB side.
Is it possible to operate FPGA in JTAG only mode or I have to use FPGA in MASTER SPI mode and generate CCLK from FPGA to CYUSB?
I have refered documents of both xilinx fpga and Cypress's CYUSB FX2LP's application note : AN61345. But I am not clear that for SLAVE FIFO mode of CYUSB; what must be FPGA's mode to be configured? For example, Can I connect SRCC or MRCC clocks from FPGA to IFCLK of CYUSB to make it operate in slave fifo mode or is it compusory to generate it from CCLK of FPGA?
https://www.cypress.com/file/44551/download
Thanks and Regards
Solved! Go to Solution.
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Hello,
On the FX2LP side any external clock frequency ranging from 5MHz to 48MHz should be fine but on the master side (FPGA) the operations should be synchronized with the IFCLK which is provided to the slave FX2LP.
Please refer to timing diagrams under slave FIFO in the FX2LP datasheet for a clear understanding of control and data signals.
Chapter 9: Slave FIFOs in EZ-USB Technical Reference Manual briefly explains the Slave FIFO mode operation of FX2LP.
Best Regards,
Yatheesh
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Hello,
The FPGA should be used in Master mode, driving the required control signals such as slave output enable, slave read, slave write etc..
If you are using external clock from the FPGA, then the clock input(IFCLK) to the EZ_USB should be between 5MHz and 48MHz and the FPGA should sample the data from FX2LP at the rate of IFCLK
This applies to both cases, when the clock source(IFCLK) is either internal or external to FX2LP.
As mentioned in AN61345 if you are using ZTEX hardware board the external IFCLK should be present before the firmware sets IFCONFIG.7 = 0 (when external clk from FPGA is used).
Best Regards,
Yatheesh
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So, is it necessary to provide IFCLK of EZ-USB from CCLK of FPGA or any bank's SRCC or MRCC clock is sufficient ?
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Hello,
On the FX2LP side any external clock frequency ranging from 5MHz to 48MHz should be fine but on the master side (FPGA) the operations should be synchronized with the IFCLK which is provided to the slave FX2LP.
Please refer to timing diagrams under slave FIFO in the FX2LP datasheet for a clear understanding of control and data signals.
Chapter 9: Slave FIFOs in EZ-USB Technical Reference Manual briefly explains the Slave FIFO mode operation of FX2LP.
Best Regards,
Yatheesh