What is the device you are using and what is the clock source?
Are there any schematic changes in your Revision 3? Can you please share your schematic once?
Have you followed the Cypress recommended schematic guidelines?
Can you please attach a demo project that reproduces the same issue/
The device is CY8C4248LQI-BL583.
There is no schematic revision just some placement change for decoupling caps on the board.
I did some more debugging. If I select ECO as the clock source, everything works fine(BLE, UART, I2C). But when I switch to IMO the whole CPU is experiencing a frequency shift of 83% of expected value. I am not sure why this issue is creeping in the current revision.
Can it be because of the power supply to IMO? which rail should I check?
Something to do with the chip lot that is present in revision 3?
Calibration of IMO?
Below is the setting that works fine
However in below setting:
BLE works but other blocks are experiencing a frequency shift of 83% of expected value.
Can someone from Cypress comment here. I checked through TRM and datasheet and unable to get a clue as to what is going wrong.
We are a very critical stage of our production.
The IMO works on the rail VDDD. Please ensure that the decoupling capacitors are correctly placed. The 0.1 uF decoupling capacitors should be placed with in 1 cm from the VDDD pins on the IC. The decoupling capacitor on the VCCD pin should be 1.3-µF capacitor.
Are there any changes in the firmware regarding the clocks?
Can you quickly program our development kit CY8CKIT-042-BLE and see whether your code is working fine? This step will tell you whether the issue is with firmware or hardware. If the project is working fine in the development kit, we will check your schematic.
If you do not have our development kit please send us the demo project that reproduces this issue for us to test here.
Thanks for the inputs. I will check for your suggestions.
Are you from Cypress India?
I can share schematics and pcb files to privately. And I can also ship one board also.
I checked the firmware by running in Pioneer board. It works as expected.
And the same firmware works as expected in my previous revision of boards.
I tried to swap PSoC IC from earlier version of working board on the faulty board.
It showed same behaviour., Everything works good on ECO. But on IMO it is giving incorrect timing.
I checked voltages on VDDD and VDDR. They are very stable and have a decoupling caps similar to Pioneer board.
Is there anything else I can look for? I think there is some trouble with the PCB/ layout/components. But if you can point to specific which components i should probe for this drift in IMO it will be helpful
"I checked the firmware by running in Pioneer board. It works as expected.
And the same firmware works as expected in my previous revision of boards."
--> This experiment says that there is no issue with the firmware. Also the previous revision of hardware is fine.
In the present hardware please check the decoupling capacitor on the VCCD pin. It should be 1.3uF .
IMO works on the Digital power supply VDDD. The output of the VDDD will be the VCCD pin.
Thanks and regards
Earlier i was confused about VCCD. I checked voltage on VCCD pin it is 2.2V in Active mode. And 1.8V in deepsleep mode.
As per datasheet it should be around 1.8V. Why is it 2.2V in my case?
The voltage on the VCCD pin should be 1.8 volts. I think the regulator inside the IC got damaged. Could you please check with different IC that gives 1.8 volts on its VCCD pin?
There may be a short circuit on the board that is causing this. Please check whether there is any connection between VCCD and VDDD when the board is not powered.
Yes, I verified the voltage on Pioneer kit it is ~1.8V.
I verified there is no short between VCCD and VDDD pin. I have personally emailed to you the design files also.
I checked with multiple custom boards. Same behavior, same voltage.
Are there any other reasons for this change in VCCD voltage?
Does this incorrect VCCD voltage explain the change in IMO frequency drift?
Why is device operating normally when using ECO instead of IMO?
And why after going into deep sleep the VCCD voltage stabilized to 1.8V?
Are there any registers present that control voltage at VCCD?
Interesting !! The voltage on the VCCD pin should be 1.8 volts if the power supply given on the VDDD pin is in the range of 1.8-5.5 volts. The VCCD voltage is the output voltage of the internal regulator. It depends only on VDDD.
The behavior of the chip will be random if the hardware specifications regarding the voltage are not met.
Do you have any un-soldered ICs with you? if yes, can you please check replacing them on the development kit and then measure the voltage? This confirms if there is any issue with the IC lot.
If you find that there is a problem with lot, please contact your distributor from whom you bought the ICs to contact Cypress and to proceed with FA case.
Thanks and regards
I took out one IC from a working board(previous revision) and put it on the revised boards. I got the same results.
The trouble lies with the board. How do I debug it.? I have verified there is no short.
I have already shared gerbers with you. Can you point out something?
1 of 1 people found this helpful
Is the IC's EPAD connected to the PCB ground? Check the connectivity between device EPAD and PCB ground.
On the PCB remove all the components related to PSoC and measure the voltages on the VDDD, VDDA and VDDR pads with respect to EPAD and PCB ground. These voltages should be same as the supply voltage.
Measure the voltage on the VCCD pad. This should be 0 without the PSoC IC.
Please check the above points and update the results to move further.