S25FL256S verilog simulation model problem

[WaHo_4359701]

Hi, can anyone help me with the spi flash verilog simulation model?

I'm using verilog behaviorial model downloaded from https://www.cypress.com/verilog/s25fl256s-verilog .

I'm having trouble understanding some code when I'm doing the simulation with my own flash controller written by Verilog.

In "s25fl256s.v" from line 3107to line 3166, as we can see below, it defines erase time(seo),erase suspend time consume(elaspsed_ers) and erase resume(which restart the erase process).From line 3142, we can see that everytime entering erase suspend, it disable the edone_process(erase done time count) and set "duration_ers = seo - elapsed_ers", from my understanding, shouldn't it be "duration_ers = duration_ers - elapsed_ers"? Because everytime entering erase suspend, duration should decline and everytime we resume erase, the duration should count from what we've suspended, but not from the start "seo".

I'm not sure if I'm getting erase suspend and resume right..?

I've already sent email to the support email  the simulation model suggested, but haven't got replies yet. Hence I ask my question here.

Hope for your reply. Thanks a lot!

[BushraH_91 · Accepted solution]

Hello Honk,

Your review of the code is correct.  The actual chip behavior is what you have understood.  This issue only impacts the simulation time performance i.e it takes longer than the actual chip.  In a real system where the status is being polled by the memory controller the memory will respond as soon as erase is done. 

Thank you

Regards,

Bushra