PSoC Creator "STA error report"

[MiNe_85951]

Hi,

I would like to confirm for STA error report at PSoC Creator.

(1)

Are there up to 10 STA errors displayed?

If there are 10 or more errors, Is it possible for us to check other errors?

(2)

If we can not confirm an error of 10 points or more,

Is it possible to mask the currently displayed errors?

(3)

Or is it possible to see the internal logic netlist?

Reagads,

[Ekta_N]

Hello Manashi,

I tried creating a project with more than than 10 STA warnings and I am able to see more than 10 warnings in the STA report generated. I am using PSoC Creator version 4.2. Can you please tell the Creator version you are using. Also if possible can you please share your project.

Best Regards

Ekta

[MiNe_85951]

Ekta-san,

Thank you for your reply.

We use PSoC Creator4.2.

I will share the project.

If you build this project, 10 warnings are displayed for STA errors.

P2[7] x3 warnings

P12[7] x3 warnings

P15[4] x2 warnings

P15[5] x1 warnings

I think it will be understood if you check the schematic of projecdt,

Not only these warned pins(P2[7], P12[7], P15[4], P15[5]) but also other similarly configured pins(P6[5:7], P2[6]) are used.
However, these pins(P6[5:7], P2[6]) do not display a warning.

So We thought that I could only display up to 10 warnings.

Regards,

Masashi

[Ekta_N]

Hello Masashi,

I tried building the project attached. I got only one warning "Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( CyBUS_CLK )."

i have attached a screenshot of the PSoC Creator page after building the project.

Best Regards

Ekta

[MiNe_85951]

I don't  know why build results are different, I will be an STA error html file.
Please could you confirm once.

[Ekta_N]

Hello Masashi,

I have attached my STA error (Static time analysis report original) html file. Can you please have a look at it and check if you are getting a similar STA error file.

Under the Time Violation section there is only one Setup time violation due to the CyBus_Clk. However under the register to register section there were multiple setup violation.

This is because a control register in PSoC 5 TM is always clocked off of BUS_CLK. This means that any other clocked circuit that it interacts with must meet timing to BUS_CLK. If you are running BUS_CLK fast, this will cause a lot of timing issues in your design

In PSoC 5 there is no synch mode for the Control register. So we need to synchronize the output of the control register with CyBus_clk using DFF as shown in the figure below.

Also, if possible you can try reducing the clock frequency. I set the clock frequency to 20 MHz and was able to fix all the warnings (STA Report with 20 MHz clock)

Best Regards

Ekta

[MiNe_85951]

Ekta-san,

Thank you for your support.

We understand that we lower the frequency of the bus clock.

And we also understood that errors of 10 points or more are also displayed.

I will confirm again there,

(2)

If we can not confirm an error of 10 points or more,

Is it possible to mask the currently displayed errors?

(3)

Or is it possible to see the internal logic netlist?

Regards,

Masashi

[Ekta_N · Accepted solution]

Hello Masashi,

(2) If there are more than 10 errors it will always be displayed in the Timing Violation Section of the STA error report.

If you need to confirm this you need to remove the currently displayed warnings and see if more warnings come up.

Please refer to the Section 5.4 of Digital design Best Practices: https://www.cypress.com/file/179061/download

(3) It is not possible to see the internal logic netlist in PSoC creator.

Best Regards

Ekta

[MiNe_85951]

Ekta-san,

These error that occurred is the return data of the bi-directional pin, so it does not affect the actual festival.

So we would like to mask the return data path.

Therefore, when using bidirectional pins,
It turns out that it is necessary to set and check each input pin and output pin.

Regards,

[Ekta_N]

Hello Masashi,

It is not possible to mask the errors from the STA report. The only way to make them disappear is to resolve them in the Project.

Best Regards

Ekta

[MiNe_85951]

Ekta-san,

We know that we can't mask unaffected signal lines.
Bidirectional pins etc. must be confirmed as input pins at the time of input and output pins at the time of output. It would be nice to have a mask function in the future.

Regards,