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Hello to everyone, I have a problem with the data bus of my FX3 - FPGA (Altera Cyclone 5) slave FIFO interface.
I used a custom firmware derived from AN65974 and continuouos read project but I need to change the data bus width from 32 to 16 bit.
I tried to edit this part of the cyfxgpif2config.h but it didn't work, when I try to transfer data with the cypress control center app the bus remains at 32bit.
This is the edited part :
/* Summary
GPIF II configuration register values.
*/
uint32_t CyFxGpifRegValue[] = {
0x80000780, /* CY_U3P_PIB_GPIF_CONFIG */
// 0x000000AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
0x00000067, /* CY_U3P_PIB_GPIF_BUS_CONFIG */ // changed to 16 bit from 32 (0xAC)
0x07000001, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
0x00000046, /* CY_U3P_PIB_GPIF_AD_CONFIG */
The question is: Do I have to edit other registers to changhe the data bus width?
thanks in advance
L.P.
Solved! Go to Solution.
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Hi,
Here are the steps:
1.Open the GPIF project provided with AN65974.
2.Select 16 bit as Data Bus width in the Interface settings. (GPIF Designer Tool)
3.Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file.
4.Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to ‘0’ in the cyfxslfifosync.h file.
5.Build the project. This step generates the image file for the 16-bit Slavefifo application.
Regards,
Rashi
Rashi
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Hi,
Here are the steps:
1.Open the GPIF project provided with AN65974.
2.Select 16 bit as Data Bus width in the Interface settings. (GPIF Designer Tool)
3.Save it and build the project by clicking Build > Build Project to generate the cyfxgpif2config.h file.
4.Set CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT to ‘0’ in the cyfxslfifosync.h file.
5.Build the project. This step generates the image file for the 16-bit Slavefifo application.
Regards,
Rashi
Rashi