4 Replies Latest reply on Jul 9, 2019 12:22 AM by SeMu_3557896

    PSoc5 LP fixed value in PERIPH memory for DMA transfer




      Because my application is requiring a lot of DMA channels, I'd like to use as much as possible different TDs rather than separated channels triggered buy TERMOUT lines.

      What I have to do: in order to transfer graphical data to a TFT display, I have to set a write strobe signal (WR) to zero, place the data on the data bus (D0-7) and then write WR back to 1.

      My intention was to use one DMA channel, with 3 TDs in order to synchronize the 3 operation in one sequence. Unfortunately, the incoming graphical data is retrieved from a flash rom via SPI (PERIPH) and goes to an 8bits control register (PERIPH) but the setting of the WR signal (via control register) would need a transfer from SRAM to PERIPH which cannot be done with the same DMA channel.

      I thought about using 2 different Status register on which I would simply connect, for one a logic 1, and for the other a logic 0: that way I could transfer from the status register (PERIPH) to the control register (PERIPH) the correct value. This doesn't work because the optimization will simply not implement the status register connected to a logical 0 (I could do it by setting unused bits to 1... but it doesn't feel very elegant).

      I'm probably doing things completely wrong… and hope someone could tell me where


      Thanks a lot for your help.