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My environment is PSoC 5LP(CY8KIT-059/CY8C5888LT) with PSoC Creator 4.2 on Window 10.
I want to read a single wired serial signal from GPIO with UDP.
First, I wrote a program that doesn't require an external input.
(*USB clock is for future implementation)
`include "cypress.v"
module data_in_test (
input data_in,
input clock,
output dma
);wire op_clk;
parameter ClockSyncMode = 1'b1;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(ClockSyncMode)) ClkSync
(
.clock_in(clock),
.enable(1'b1),
.clock_out(op_clk)
);localparam RG_IDLE = 3'b000;
localparam RG_SHIFT = 3'b001;
reg [2:0]rg_state;reg dp_f0_load;
reg[2:0] state;
reg[3:0] ct;wire dp_si;
reg dp_si_reg;
assign dp_si = dp_si_reg;always @(posedge op_clk)
begin
dp_si_reg <= ~dp_si_reg;
dp_f0_load <= 1'b0;
rg_state <= RG_SHIFT;
ct <= ct + 1'b1;
if(ct == 1'b0)
begin
dp_f0_load <= 1'b1;
end
endcy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
}
)) dp(
.reset(1'b0),
.clk(op_clk),
.cs_addr(rg_state),
.route_si(dp_si),
.route_ci(1'b0),
.f0_load(dp_f0_load),
.f1_load(1'b0),
.d0_load(1'b0),
.d1_load(1'b0),
.f0_bus_stat(dma),
.f0_blk_stat(),
.f1_bus_stat(),
.f1_blk_stat()
);
endmodule
#include "project.h"
#include <stdio.h>/* Defines for data_in_dma */
#define data_in_dma_BYTES_PER_BURST 1
#define data_in_dma_REQUEST_PER_BURST 1
#define data_in_dma_SRC_BASE (CYDEV_PERIPH_BASE)
#define data_in_dma_DST_BASE (CYDEV_SRAM_BASE)/* Variable declarations for data_in_dma */
/* Move these variable declarations to the top of the function */
uint8 data_in_dma_Chan;
uint8 data_in_dma_TD[1];#define COUNT 256
uint8 res_buffer[COUNT];void InitDma()
{
/* DMA Configuration for data_in_dma */
data_in_dma_Chan = data_in_dma_DmaInitialize(data_in_dma_BYTES_PER_BURST, data_in_dma_REQUEST_PER_BURST,
HI16(data_in_dma_SRC_BASE), HI16(data_in_dma_DST_BASE));
data_in_dma_TD[0] = CyDmaTdAllocate();
CyDmaTdSetConfiguration(data_in_dma_TD[0], COUNT, data_in_dma_TD[0], data_in_dma__TD_TERMOUT_EN | CY_DMA_TD_INC_DST_ADR);
CyDmaTdSetAddress(data_in_dma_TD[0], LO16((uint32)data_in_test_1_DMA_PTR), LO16((uint32)res_buffer));
CyDmaChSetInitialTd(data_in_dma_Chan, data_in_dma_TD[0]);
CyDmaChEnable(data_in_dma_Chan, 1);
}int out_once_check = 0;
CY_ISR(OnInterruptPaInDma)
{
if(out_once_check) return;
out_once_check = 1;
for(int n = 0; n < COUNT; n++){
for(int m=0;m<8;m++){
UART_PutChar(((res_buffer>> (7-m)) & 0x1) ? '1' : '0');
}
UART_PutChar('\n');
}
}int main(void)
{
CyGlobalIntEnable;isr_dma_StartEx(OnInterruptPaInDma);
InitDma();
UART_Start();for(;;)
{
}
}
It works well.
Next, I sent a signal of 6 MHz to P3[0] pin like this.
This is a sample of the result.
Considering that a clock source for sync is 24 MHz the same value should continue for two(110011110011...) even if there is a slight synchronization deviation. That is, it can't acquire data by a sync clock. I also connected PSoC standard filter and sync components, but there was no effect.
This is a full project on OneDrive. Please tell me what is missing in my project
Solved! Go to Solution.
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tayuc,
I am thinking of different approach: the PSoC5 PLL can be locked to incoming external 6MHz SPDIF signal, then the data can be read directly using FIFO buffer and DMA. This is just an idea.
/odissey1
P.S. I tried to lock PSoC5 PLL to external SPDIF signal (clocked at 6MHz). The resulting PLL output frequency got same as the input, but does not phase-lock to ~2MHz SPDIF signal due to high instability of the signal. Reducing PLL current down to 1uA hepls, but PSoC5 has no lower current settings. I see potential solution using external 4046 PLL for extracting 6MHz carrier from SPDIF signal and then locking PSoC5 PLL to that carrier.
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I have a comment to your code.
reg[3:0] ct;
:
always @(posedge op_clk)
:
begin
ct <= ct + 1'b1;
if(ct == 1'b0)
begin
:
end
end
At first you declare the register ct as reg[3:0] the ct becomes a 4-bit register.
You compare the register ct with 1'b0, but 1'b0 is expanded to 4-bit 4'b0000 as well as the incrementa 1'b1 is expanded to 4'b0001 i line 06
As the result the line 09 is executed every 16 clocks because ct is declared as 4-bit register.
If you want to assert f0_load every 8 clocks, Use 3-bit register as ct.
Regards,
Noriaki
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TaYu,
It seems that you are trying to read a serial signal. Did you try to use a standard UART? With oversampling 8x it should handle 6MHz carrier.
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Originally is S/PDIF. I tried with 12.288MHz crystal x4 PLL referring to Cypress's SPDIF_Tx sample includes in PSoC Creator, but failed.
For this reason, to make a program that solves this noise, I use pseudo signals instead of.
> reg[3:0] the ct becomes a 4-bit register.
It's my easy mistake. thanks for your advice.
I uploaded a latest archive. A result is close to that in the logic analyzer, but it still contains noise.
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tayuc,
I am thinking of different approach: the PSoC5 PLL can be locked to incoming external 6MHz SPDIF signal, then the data can be read directly using FIFO buffer and DMA. This is just an idea.
/odissey1
P.S. I tried to lock PSoC5 PLL to external SPDIF signal (clocked at 6MHz). The resulting PLL output frequency got same as the input, but does not phase-lock to ~2MHz SPDIF signal due to high instability of the signal. Reducing PLL current down to 1uA hepls, but PSoC5 has no lower current settings. I see potential solution using external 4046 PLL for extracting 6MHz carrier from SPDIF signal and then locking PSoC5 PLL to that carrier.
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Dear BoTa.
It's very helpful how to create a clock with 74HC4046.
The pseudo signal has a limit in development. So I created an environment that receiving the actual 48KHz audio signal with 12.288 MHz crystal. However, PSoC seems to be operating at a different frequency than the clock source(Both XTAL / Digital Signal).
This is an issue about a clock generator not UDP, so I'll ask about this at a new thread if necessary.