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Chip is not writing to the FLASH location .
I am using NOR FLASH S29GL256S10DHV020 and programming a FLASH BYTE . using following steps , but non of the data is written .
uint16_t *base_addr = (uint16_t *)0x60000000;
uint16_t *pa = (uint16_t *)0x60000100;
uint16_t data = 0x1234;
*( (uint16_t *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (uint16_t *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (uint16_t *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (uint16_t *)pa ) = data; /* write data to be programmed */
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Hi,
I would like to get some more details about this issue. Please provide below information.
1. Are you making sure that the program operation is finished either by reading status register or by data polling as mentioned in the datasheet?
2. Are you performing programming operation on an erased sector?
Thanks and Regards,
Sudheesh
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I am Erasing entire 32MB Flash before writing to the NOR FLASH .
/* Erase entire flash. */
void eraseFlash(void)
{
unsigned int j;
flashwrite(CMDADDR(0x555), 0xAA); /* 6 cycle chip erase command */
for ( j = 0 ; j < 2; j++);
flashwrite(CMDADDR(0xAAA), 0x55);
for ( j = 0 ; j < 2; j++);
flashwrite(CMDADDR(0x555), 0x80);
for ( j = 0 ; j < 2; j++);
flashwrite(CMDADDR(0x555), 0xAA);
for ( j = 0 ; j < 2; j++);
flashwrite(CMDADDR(0xAAA), 0x55);
for ( j = 0 ; j < 2; j++);
flashwrite(CMDADDR(0x555), 0x10);
for ( j = 0 ; j < 2; j++);
while (flashread(FLASHADDR) != 0xFFFFFFFF);
}
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Hi,
Please remove the check for timeout from the function "_FLASH_waitWhileProgramming". You should implement the data polling as per table 5.3 of the datasheet (https://www.cypress.com/file/177976/download ) to check the completion status of program/erase operations and to check the errors occurred. Also, you should check the completion status after erase operation also.
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
Do you have working source code that you can share to me or Example Source files for the mentioned Implementation method .
We have to release an 32 MB supported board to customer by July 15th and with current driver implementation I am not able to write or read to NOR flash .
I need these source code driver to write and Read from the S25FL256LAGMFB000.
It will help in releasing a working code to ,Can you share me if already implemented driver code in C language is available .
implement the data polling as per table 5.3 of the datasheet (https://www.cypress.com/file/177976/download ) to check the completion status of program/erase operations and to check the errors occurred. Also, you should check the completion status after erase operation also.
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Hi,
I hope you are using both serial (S25FL256LAGMFB000) and parallel (S29GL256S10DHV020) flash devices in your application. Please see our low level driver for our serial flash devices attached with this response. LLD for our parallel NOR flash is available at following link: https://www.cypress.com/documentation/software-and-drivers/low-level-driver-nor-flash?source=search&... .
Thanks and Regards,
Sudheesh
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Thanks for sending the Drivers ,
I will keep you updated .
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Does Cypress sell any development kit that has256Mbit Parallel NOR flash.
we are using LLD and trying to write and read back on our board but not able to get any working mode.
our microcontroller is TMS570LS3137 and we are unable to probe signals as it is BGA
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Hi,
Can you attach your source code to this forum thread? We can review and let you know, if there are any issues.
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
The Attached .zip file is has the complete TMS570LS3137 EMIF related project .
The SDRAM IS45S16320F-7BLA2 Connected to EMIF on the board is "working perfectly".The source code for SDRAM is emif.c emif_SDRAM_StartupInit() and sys_main.c sdram_main() .
For S29GL256S10DHV020 Nor_Flash in the main() function call , reading device ID with API lld_GetDeviceId() ,.
Read values of WAFER_LOT and CLASS_LOT returns 0x00000000FFFFFF00 (Hex) .
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Hi Sudheesh ,
Should the WAVEFORM help in debugging the NOR FLASH .
I have captured the following signals for NOR FLASH and SDRAM .
0- CS2
1- EMIF_n_Wait
2- EMIF_WE
3- EMIF_OE
4- EMIF_D0
5- EMIF_A0
6- EMIF_A1
WAVEFORM DURING NOR FLASH SOURCE CODE ACCESS
WAVEFORM DURING SDRAM SOURCE CODE ACCESS
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Hi,
Can you let us know more details about how the address signals are connected to the controller? Can you share your complete schematic with us? We see that S_EMIF_BA0 and S_EMIF_BA1 signals are connected to the flash address signals. What are these signals?
How is the controller address space organized? Does the controller address bytes or words (16 bits)? Please clarify.
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
The EMIF Part of the TMS570LS3137 connections are as follows .
32MB S29GL256S10DHV020 Nor_Flash
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Additional Details of EMIFBE1 and EMIFBE0 are on Page 14 of https://training.ti.com/system/files/docs/keystone-external-memory-interface-user-guide.pdf
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Hi,
Could you please let us know the value configured in register CE2CFG? Please make sure that the field ASIZE in this register is configured for 16 bit bus.
Thanks and Regards,
Sudheesh
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Hi ,
Yes the value configured in register CE2CFG for ASIZE in this register is configured for 16 bit bus .
void emif_ASYNC2Init(void)
{
/* USER CODE BEGIN (6) */
/* USER CODE END */
emifREG->CE3CFG = 0x00000000U;
emifREG->CE3CFG = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)0U << 30U)|
(uint32)((uint32)14U << 26U)|
(uint32)((uint32)110U << 20U)|
(uint32)((uint32)110U << 17U)|
(uint32)((uint32)14U << 13U)|
(uint32)((uint32)110U << 7U)|
(uint32)((uint32)110U << 4U)|
(uint32)((uint32)0U << 2U)|
(uint32)((uint32)emif_16_bit_port);
emifREG->AWCC = (emifREG->AWCC & 0xC0FF0000U)|
(uint32)((uint32)emif_pin_low << 29U)|
(uint32)((uint32)emif_pin_low << 28U)|
(uint32)((uint32)emif_wait_pin1 << 18U)|
(uint32)((uint32)2U);
emifREG->PMCR = (emifREG->PMCR & 0xFFFF00FFU)|
(uint32)((uint32)0U << 10U)|
(uint32)((uint32)emif_8_words << 9U)|
(uint32)((uint32)0U << 8U);
/* USER CODE BEGIN (7) */
/* USER CODE END */
}
One Additional Query is for the LLD driver I am selecting following configuration . Is this configuration correct for our Hardware .
#define LLD_CONFIGURATION_X32_AS_X32 /* no-interleaving, a single x32 device in x32 mode */
The following SDRAM is also connected on the Hardware that works perfectly . The BA0 and BA1 will be used different functionality on the SDRAM .
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Yes the value configured in register CE2CFG for ASIZE in this register is configured for 16 bit bus .
void emif_ASYNC1Init(void)
{
/* USER CODE BEGIN (4) */
/* USER CODE END */
emifREG->CE2CFG = 0x00000000U;
emifREG->CE2CFG = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)0U << 30U)|
(uint32)((uint32)14U << 26U)|
(uint32)((uint32)110U << 20U)|
(uint32)((uint32)110U << 17U)|
(uint32)((uint32)14U << 13U)|
(uint32)((uint32)110U << 7U)|
(uint32)((uint32)110U << 4U)|
(uint32)((uint32)0U << 2U)|
(uint32)((uint32)emif_16_bit_port);
emifREG->AWCC = (emifREG->AWCC & 0xC0FF0000U)|
(uint32)((uint32)emif_pin_low << 29U)|
(uint32)((uint32)emif_pin_low << 28U)|
(uint32)((uint32)emif_wait_pin1 << 16U)|
(uint32)((uint32)2U);
emifREG->PMCR = (emifREG->PMCR & 0xFFFFFF00U)|
(uint32)((uint32)0U << 2U)|
(uint32)((uint32)emif_8_words << 1U)|
(uint32)((uint32)0U);
/* USER CODE BEGIN (5) */
/* USER CODE END */
}
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Hi,
Thank you for the details. The CE2CFG configuration looks OK. As S29GL256S is a single x16 device, you should be using below configuration in LLD,
"#define LLD_CONFIGURATION_X16_AS_X16 /* no-interleaving, a single x16 device in x16 mode */"
NOT "#define LLD_CONFIGURATION_X32_AS_X32 /* no-interleaving, a single x32 device in x32 mode */"
Please make the change and let us know, if you can access our flash device.
Thanks and Regards,
Sudheesh
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The NOR FLASH device is not responding With the applied configuration
"#define LLD_CONFIGURATION_X16_AS_X16 /* no-interleaving, a single x16 device in x16 mode */"
Can you confirm the following values for NOR FLASH
the EMIF clock is configured at 90 MHz .
WRITE_SETUP
WRITE_STROBE
WRITE_HOLD
READ_SETUP
READ_STROBE
READ_HOLD
Should Select Strobe Mode turned ON ?
Extended Wait required tobe ON?
Tavav is 110 ns
Tehel is 20 ns
Are these correct timings
Write setup = 2h
Write strobe = 6h
Write hold = 1h
Read setup = 1h
Read Strobe = 11 h
Read hold= 3h
TA= 3h
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Hi,
Your read/write timing configuration look OK.
Write setup = 2h
Write strobe = 6h
Write hold = 1h
Read setup = 1h
Read Strobe = 11 h
Read hold= 3h
TA= 3h
Can you provide more details about "The NOR FLASH device is not responding With the applied configuration"? What is the data that you read from flash device using function "lld_GetDeviceId()"?
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
Appreciate your support on the NOR FLASH issue .
My Explanation was not with enough Clarity .
The address 0x60000000 can be read as all values set to 0xFFFF ( these values should be the default erase values on the CHIP ).
Any read to the Address 0x60000000 to 32 MB returns 0xFFFF .
The lld_GetDeviceId() also returns 0xFFFF . Attached images debug window explains the values being read as 0xFFFF .
I am also sharing the source code in Gdrive , if you have any other services to share the source files do let me know I will share trough that means .
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Hi,
Can you share the waveform for a single read and write operation to the flash device? Can you capture all the signals between controller and flash device and send to us, if you have a logic analyzer? If you do not have a logic analyzer, please capture below signal for read and write operations respectively.
Read operation: BA1 (A0 of flash), A0 (A1 of flash), A1 (A2 of flash), CE#, OE#, DQ0, DQ1
Write operation: BA1 (A0 of flash), A0 (A1 of flash), A1 (A2 of flash), CE#, WE#, DQ0, DQ1
Thanks and Regards,
Sudheesh
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Hi ,
I Cannot Access the Exact Lines what you have requested on the Production Board . We have and TMS570LS3137 HDK that has access to all lines . There are differences from what you have requested .
base_addr is 0x60000000
SCOPE PLOT 1:
FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x00000555)))) = (((0xAA)*0x00000001))
Write operation: BA1 (A0 of flash), A0 (A1 of flash), A1 (A2 of flash), A2 (A3 of flash), CS2, WE#, DATA0, DATA1
void emif_ASYNC2Init(void)
{
emifREG->CE3CFG = 0x00000000U;
emifREG->CE3CFG = (uint32)((uint32)1U << 31U)|
(uint32)((uint32)0U << 30U)|
(uint32)((uint32)2U << 26U)|
(uint32)((uint32)6U << 20U)|
(uint32)((uint32)1U << 17U)|
(uint32)((uint32)1U << 13U)|
(uint32)((uint32)11U << 7U)|
(uint32)((uint32)3U << 4U)|
(uint32)((uint32)3U << 2U)|
(uint32)((uint32)emif_16_bit_port);
emifREG->AWCC = (emifREG->AWCC & 0xC0FF0000U)|
(uint32)((uint32)emif_pin_low << 29U)|
(uint32)((uint32)emif_pin_low << 28U)|
(uint32)((uint32)emif_wait_pin1 << 18U)|
(uint32)((uint32)0U);
emifREG->PMCR = (emifREG->PMCR & 0xFFFF00FFU)|
(uint32)((uint32)0U << 10U)|
(uint32)((uint32)emif_8_words << 9U)|
(uint32)((uint32)0U << 8U);
}
ZOOM 100x
SCOPE PLOT 2:
FLASH_WR(base_addr, LLD_UNLOCK_ADDR2, NOR_UNLOCK_DATA2);
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x000002AA)))) = (((0x55)*0x00000001))
Zoom In 100x
Read operation: BA1 (A0 of flash), A0 (A1 of flash), A1 (A2 of flash), A2 (A3 of flash), CS2, OE#, DQ0, DQ1
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x008E))))
ZOOM 100x
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Above mentioned Scope plots are with Strobe Mode ON .
SECTION : Following are Scope plots with Strobe Mode OFF
void emif_ASYNC1Init(void)
{
emifREG->CE2CFG = 0x00000000U;
emifREG->CE2CFG = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)0U << 30U)|
(uint32)((uint32)2U << 26U)|
(uint32)((uint32)6U << 20U)|
(uint32)((uint32)1U << 17U)|
(uint32)((uint32)1U << 13U)|
(uint32)((uint32)11U << 7U)|
(uint32)((uint32)3U << 4U)|
(uint32)((uint32)3U << 2U)|
(uint32)((uint32)emif_16_bit_port);
emifREG->AWCC = (emifREG->AWCC & 0xC0FF0000U)|
(uint32)((uint32)emif_pin_low << 29U)|
(uint32)((uint32)emif_pin_low << 28U)|
(uint32)((uint32)emif_wait_pin1 << 16U)|
(uint32)((uint32)0U);
emifREG->PMCR = (emifREG->PMCR & 0xFFFFFF00U)|
(uint32)((uint32)0U << 2U)|
(uint32)((uint32)emif_8_words << 1U)|
(uint32)((uint32)0U);
}
FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x00000555)))) = (((0xAA)*0x00000001))
Write operation:
SIGNAL 0 = BA1 (A0 of flash),
SIGNAL 1 = A0 (A1 of flash),
SIGNAL 2= A1 (A2 of flash),
SIGNAL 3= A2 (A3 of flash),
SIGNAL 4= CS2,
SIGNAL 5= WE#,
SIGNAL6= DATA0,
SIGNAL7 = DATA1
SCOPE PLOT 2:
FLASH_WR(base_addr, LLD_UNLOCK_ADDR2, NOR_UNLOCK_DATA2);
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x000002AA)))) = (((0x55)*0x00000001))
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Hi,
Thank you for the waveform for write and read operations. We observed that there is 3 write cycles corresponding to a single write command. Please see below.
This is the scope shot that you attached for below write operation in the source code.
FLASH_WR(base_addr, LLD_UNLOCK_ADDR1, NOR_UNLOCK_DATA1);
(*(( (volatile FLASHDATA*)((base_addr)) ) + ((0x00000555)))) = (((0xAA)*0x00000001))
Please clarify, why there are 3 write cycles (WC1..3) for a single write operation?
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
Thanks for Mentioning this Finding .
Please give some time to get the response from Texas Instruments . As I am following what Texas instruments is suggesting to implement the EMIF Initialization steps.
Thanks and Warm Regards ,
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Hi Sudheesh ,
I will tomorrow work on the LLD migration to our project . I was able to fix the WE# issue on the EMIF and able to read following data from NOR FLASH .
I will have to verify the timings and also the consistency of writes and read to NOR FLASH tomorrow .
at 45MHz EMIF clock frequency I have set following values , can you confirm if these are correct .
emifREG->CE2CFG = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)0U << 30U)|
(uint32)((uint32)8U << 26U)| // Write Setup
(uint32)((uint32)24U << 20U)| // Write Strobe
(uint32)((uint32)4U << 17U)| // Write Hold
(uint32)((uint32)4U << 13U)| // Read Setup
(uint32)((uint32)44U << 7U)| // Read Strobe
(uint32)((uint32)12U << 4U)| // Read Hold
(uint32)((uint32)12U << 2U)| // TA
(uint32)((uint32)emif_16_bit_port);
Following are 2 screenshots of the NOR FLASH
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Hi,
Register settings looks OK. Please let us know the test results, if you face any issues.
Thanks and Regards,
Sudheesh
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Hi Sudheesh ,
I have implemented Read Device ID using Common FIash Interface and also to ERASE SECTOR and Write data to FLASH .
For all these I have used Delay mechanism and would like to know how to get the status bit read correctly done .
I tried to use Status bit read while writing to NOR FLASH but it never returns correct status .
Following is the implementation with delays that work.
// SECTOR ERASE
// COMPLETE CHIP ERASE COMMAND REQUIRES 70 SECODNS
{
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0x80)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) )) = (((0x30)*0x00000001)); // SECTOR ERASE
//(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0x10)*0x00000001)); // CHIP ERASE
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
for(delay=0;delay<65535;delay++);
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001));
}
for(Read=0;Read<19;Read++) // read DEVICE ID by CFI
{
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0x90)*0x00000001));
Device_ID[Read] = (unsigned char)((*(( (volatile unsigned short*)((0x60000000)) ) + ((0x0080+Read)))) & 0x000000FF) ;
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001));
}
//lld_ProgramCmd(base_address_nor_flash,offset++,source_address++);
for(Write_Nor=0;Write_Nor<65535;Write_Nor++)
{
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xA0)*0x00000001));
((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Nor)))))= Write_Nor;
for(delay=0;delay<5000;delay++);
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001));
}
I am using following to check the status of write process :-
#define DEV_RDY_MASK (0x80*0x00000001) /* Device Ready Bit */
FLASHDATA lld_Poll
(
FLASHDATA * base_addr, /* device base address in system */
ADDRESS offset /* address offset from base address */
)
{
unsigned long polling_counter = 0xFFFFFFFF;
volatile FLASHDATA status_reg;
do
{
polling_counter--;
lld_StatusRegReadCmd( base_addr ); /* Issue status register read command */
status_reg = FLASH_RD(base_addr, offset); /* read the status register */
if( (status_reg & DEV_RDY_MASK) == DEV_RDY_MASK ) /* Are all devices done bit 7 is 1 */
break;
}while(polling_counter);
return( status_reg ); /* retrun the status reg. */
}
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Hi Sudheesh ,
I need help with Buffer Writing to Flash algorithm Page 43 of CYPRESS S29GL256S NOR FLASH .
Following code is as per LLD driver I am using and for 1st time the 512 Bytes is getting written to FLASH .
second time the write fails to write the 512Bytes so on .
for(Write_Nor=0;Write_Nor<0x100;Write_Nor++)
{
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
// Write to Buffer
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((Count_Words)))) = (((0x25)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((Count_Words)))) = 128; // writing 128 bytes at a time to buffer
for(Write_Buffer=0;Write_Buffer<256;Write_Buffer++)
{
((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words)))))= 0xABCD;
}
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
// Write from Buffer to NOR Flash 512 Bytes
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000000))+((Count_Words)))) = (((0x29)*0x00000001)); // program buffer to flash
for(delay=0;delay<5000;delay++); // 4000 * 30 ASM instructions * 5.55 nano seconds = 660000 nano seconds
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
Count_Words+=512;
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
}
Attached is the NOR FLASH data written details .
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Additional details of EMIF_BA1 and EMIF_BA0 can be found in page 622 & 637 of
TMS570LS31x/21x 16/32-Bit RISC Flash
Microcontroller
Technical Reference Manual
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Hi Sudheesh ,
No the status register is not being read .
Yes , the Wait cycles code is as follows . I can send the source .c and .h file I am using , I do not have the upload details .
if ( _FLASH_waitWhileProgramming( ( uint32_t )pdst16, full_word_to_write, timeout ) )
/* ------------------------------------------------------------------------ *
* *
* FLASH_waitWhileProgramming( ) *
* *
* Wait while programming ( SPANSION Flash ) *
* *
* ------------------------------------------------------------------------ */
uint16_t _FLASH_waitWhileProgramming( uint32_t addr, uint16_t data, uint32_t timeout )
{
uint16_t* pdata = ( uint16_t* )addr;
while ( --timeout > 0 )
if ( *pdata == data )
return 0; /* Good, programming completed */
/* Timeout occured */
FLASH_BASE_PTR8 = FLASH_RESET;
return 1;
}
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Hi,
As per my understanding, you were able to perform write buffer program operation twice successfully and it failed from third time onward. Is my understanding correct? Are you polling status register after every write to buffer program operation to make sure device is not busy before next program operation? Can you please let me know the value in status register when this failure happens?
Thanks and Regards,
Sudheesh
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Hi ,
Yes your Understanding is Correct .
I am confirming to write 256 Bytes from buffer to Flash 2 time total of 512 Bytes are written to NOR FLASH , The third time the device gets locked or some status that I HAVE to recover the device only with power restart .
Does Cypress provide and API that has the Buffer based programming implemented .
I must be doing wrong with API implementation . could not verify if the polling method I implemented is correct
The source code is as follows .
for(Write_Nor=0;Write_Nor<0x10000;Write_Nor++)
{
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
// Write to Buffer
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000555)))) = (((0xAA)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x000002AA)))) = (((0x55)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((Count_Words)))) = (((0x25)*0x00000001));
(*(( (volatile unsigned short*)((0x60000000)) ) + ((Count_Words)))) = 128; // writing 128 bytes at a time to buffer
for(Write_Buffer=0;Write_Buffer<128;Write_Buffer++)
{
((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words)))))= 0xABCD;
}
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
// Write from Buffer to NOR Flash 256 Bytes
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0x00000000))+((Count_Words)))) = (((0x29)*0x00000001)); // program buffer to flash
// Keep Polling for status Do not know if the polling method I implemented is correct
while((((Status_read=((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words))))))) & 0x80) == 1);
while((((Status_read=((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words))))))) & 0x40) == 1);
while((((Status_read=((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words))))))) & 0x02) == 1);
while((((Status_read=((*(( (volatile unsigned short*)((0x60000000)) ) + ((Write_Buffer))+((Count_Words))))))) & 0x80) == 1);
// additional delay time if polling fails
for(delay=0;delay<10000;delay++); // 10000 * 30 ASM instructions * 5.55 nano seconds = 1665000 nano seconds
// Reset command
(*(( (volatile unsigned short*)((0x60000000)) ) + ((0)))) = (((0xF0)*0x00000001)); // Reset Command
Count_Words+=128;
}
Image step 1 after full CHIP ERASE FUNCTION:
Image step 2 after 1st time 256 bytes writing:
Image step 3 after 2nd time 256 bytes writing:
Image step 4 after device gets locked:
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Hi,
Sorry for the delay. Implementation of polling doesn't look correct. Please check the table "Table 5.3 Data Polling Status" given on page 39 of the datasheet, https://www.cypress.com/file/177976/download . You have to read continuously and check the data lines (DQ7, DQ6, DQ5, DQ3, DQ2, DQ1) to know the device status.
Error conditions for write buffer programming operations are given in the last row of this table.
Thanks and Regard,s
Sudheesh