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Hello,
I tried whether Program counter is jumped to Hard Fault or NMI if PSoC4S runs in the unused flash area like
"Execution of an Undefinded instruction" of Cortex™-M0+ Devices Generic User Guide(ARM DUI 0662B).
The unused flash area is filled 0x00 by Compiler(Linker?) of PSoC Creator.
I launched the debugger and breaked after running. Then I changed PC(Program Counter) to the unused flash area.
After that, I ran it again. Consequently, PC is running in the while(1) of CY_ISR(IntDefaultHandler) in Cm0plusStart.c.
The errno macro seems to mean 0 value. but, there is no 0 value in "errno.h".
Does it mean that "Execution of an Undefinded instruction" is done?
Best regards,
Yocchi
Solved! Go to Solution.
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if you have not modify "Cm0plusStart.c", Ram Interrupt vector is used.
And, "IntDefaultHandler" function is registered for all exceptions except "Rest".
if you faces an exception (i.e. "IntDefaultHandler" is called), you can see xPSR register in "IntDefaultHandler" to understand what happened.
I think HardFault would be occurred in your case.
Regarding xPSR register, please refer to the ARM documentation or PSoC 4S Architecture TRM.
https://www.cypress.com/file/230701/download
Table 4-3. Cortex-M0+ PSR Bit Assignments
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Hello,
I think that it might be processing by debugger.
Best regards,
Yocchi
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Apology for late response...
Could you please let us know where "errno.h" comes from?
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if you have not modify "Cm0plusStart.c", Ram Interrupt vector is used.
And, "IntDefaultHandler" function is registered for all exceptions except "Rest".
if you faces an exception (i.e. "IntDefaultHandler" is called), you can see xPSR register in "IntDefaultHandler" to understand what happened.
I think HardFault would be occurred in your case.
Regarding xPSR register, please refer to the ARM documentation or PSoC 4S Architecture TRM.
https://www.cypress.com/file/230701/download
Table 4-3. Cortex-M0+ PSR Bit Assignments