Getting interrupt or other internal signals out on pin

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OlPe_282281
Level 2
Level 2
Welcome! 10 replies posted 5 replies posted

Hello,

for realtime control I need to route/connect a signal, e.g. interrupt signal from MFT/FRT zero match, to a physical pin. The intension is to have to possibility to check the timing behaviour (with respect to e.g. jitter) using an oscillocope without software interaction (no pin toggling inside an ISR etc.). In this example the signal shall act as scope trigger und time slice reference.

How get this as it is possible at least at e.g. Cypess psoc{3,5,..} using PSoC Creator schematics.

Thanks.

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ShipingW_81
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

It's easy to get internal interrupt out on a physical pin using PSoC. However,  just from your description, it seems hard to get the specific purpose which you plan to achieve on e.g. PSoC3/5.

Can you tell more about the use of the signal routed from internal MFT/FRT to a physical pin, and what's your corrent concern "the intension"?

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attached the current state of the FM4 S62CC Pioneer Kit specific part of the project. I'm using IAR Workbench/ARM 8.32 with PDL 2.1.0. The project shall control a BLDC later on (different approach as Park/Clark transformation; BTW: unfortunately, the AN202488 doesn't use the PDL ...), hence use of ADC (not yet here) and 3-phase PWM (here I am).

The relevant part is at CyFM4/ConfigMFT. It it configured to call the ISR for PeakMatch (and not of interest e.g. Zero Match) which calls controlMain() (located in main.c for my convinience).

The idea is to see hardware signals (interrupts, FRT zero-match etc, ADC sampling) without software interaction (as of PSoC Creator's schematic way wiring the signals to pins). Following my Boss some uC support to connect these signals to I/O pins. This gives the possibility to check hard realtime timing behaviour. Also, to see the time points where e.g. the ADC does sample. Simply setting the 'logging' pins inside IRQ callbacks introduce some delay from calling the ISR self (depends on priority etc.) and CPU clock cycles. Using the software toggle gives software jitter shown on scope whch isn't intended. It's thinking more in synchronuous hardware as of software. Hopefully my intention is more clear now.

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We would like to recommend you to adopt PSoC device for any new design, as the tech support resource is very limited for FMx device.

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