how can I send data from SPIS to SPIM?

[DaCh_4286001]

The practice is: on same chip. I will send data from SPIM and read data back from SPIS.

I know SS line is controlled by SPIM, only when SPIM Tx FIFO NOT EMPTY, SS line will go low and allow transmission from SPIM to SPIS.

By default,  it will force the SPIS "Interrupt on RX FIFO Not empty" to be on. After one byte is send from SPIM into SPIS RX FIFO , interrupt will be triggered, SPIS Rx will read data in Rx FIFO and move it into SPIS Rx Buffer, then SPIS Rx FIFO is empty now. All other processes are blocked during this interrupt.

My question is:

Now I am sending 10 bytes using SPIM_writeData(), I want slave to send back data starting from the 6th charater it receives in Rx Bxffer.

in the SPIS_Rx_Not_empty ISR, in /* User code required at end of ISR (Optional) */ section, if I add SPIS_Write_data ('a' ) in it, why  I cannot send data back to master?

Simon

[Bob_Marlowe · Accepted solution]

For every bit (byte) the SPI interface gets, one bit (byte) is returned immediately. When the very first byte is sent, the interface does not "know" yet what to answer, so a dummy byte is returned which should be skipped.

SPI has no read command, so you must send dummy bytes to retrieve the information wanted.

A pitfall is the select line, which is automatically taken low when a byte is sent. When the buffer is empty it is taken high again. This can lead to interface errors when the byte sequence is not provided fast enough resulting in ss-line glitches.

Keep in mind that there is no SPIS - send command, always the SPIM has to send data.

Bob

[DaCh_4286001]

Then what is SPIS_WriteData do? Isn't this writing data from slave to master when ss line is low?

[Bob_Marlowe]

No, it just puts a byie into the transmit buffer. The master still needs to send a (dummy) byte to transmit it.

Bob