clock stops!

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JoWi_3984961
Level 4
Level 4
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How good is the phase locked loop on the PSOC 4?

I'm seeing clock stop for a tiny bit every so often.

I see you have an issue here:

Output behavior of CY22393 (or CY22381, CY22392, CY22394, CY22395) in case of lost reference clock o...

But, is the same IP used in the phase locked loop on PSOC 4?

I only change the divisor and the fractional divisor.

I never stop it.

It is set to start up automatically in the system-wide resources.

Is there an errata on this? An application note? Any document?

What if we reference our clock to a USB device?

A crystal?

Which is most reliable?

Need some external reference.

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JoWi_3984961
Level 4
Level 4
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can a usb trim state cause a 1/(48,000,000/64k) second resync timeout?

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JoWi_3984961
Level 4
Level 4
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What if I change the frequency using the api?  Will it have a dead-time of over a ms?

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So is it really required to stop the clock, just to change the frequency?  Or just figure it might not run past the trigger point and run

through the entire counter (1.3 ms of dead time)?  Is it best to reduce this possibility by stopping the clock, changing the freq, and then starting it?

It seems so to me.

So, it seems it IS required to stop the clock if you want a clean change of freq.

But, if you stop the clock.. [catch 22]

Anyone have a better answer?

Thanks!

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Hi,

Could you please elaborate what is [catch 22]. And what all are the issues you are facing if you stop and start the clock

Thanks

Ganesh

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I want no glitch

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