Hi,
I have a simple application that FPGA(Master) keep sending data to FX3(Slave) @12.5Mhz.
Data could be seen by running similar <gpiftousb> sample, all I need to do right now is to add CLK signal and change GPIF as slave for synchronization.
I modified the original GPIFII configuration as below:
State machine configuration remains unchanged:
And copied the new header file to original firmware project, nothing else changed.
Right now I can only read 16K data for 8 times: (Match with the 4 x 32K DMA buffers), then error will occur.
By printing the state machine status from UART port,
I could see it starts from 0(START), and jumps to 1(DMAWAIT), then to 2(READDATA), and back to 1(DMAWAIT), which seems reasonable,
but the problem is it always stuck as 1(DMAWAIT) after this and will never go back to 2(READDATA), even after the PC has read out all the data from the buffer,
Looks like the DMA_RDY_TH0 flag does not go high again as it supposed to.
It's there anything else needed to be configured or any suggestions? Thanks in advance!
Best Regards,
Kevin
