SPIS_GetRxBufferSize()

Hi Simon,

If the Rx_buffersize is 0 when you read SPIS_GetRxBufferSize(), I think it is possible that you have cleared your Rx buffer in your code.

Could you show us the function: SPIM_ReadTxStatus() ？

Suggestions:

You can design the logic of the program like this：

    /* Start transfer */
    SPIM_SpiUartPutArray(dummyBuffer, PACKET_SIZE);

    /* Wait for the end of the transfer. The number of transmitted data
    * elements has to be equal to the number of received data elements. */
    while (PACKET_SIZE != SPIM_SpiUartGetRxBufferSize());

    /* Clear dummy bytes from TX buffer */
    SPIM_SpiUartClearTxBuffer();

Please let me confirm if you connect interface signals of two components SPIM and SPIS.

Please refer "SPI_Design" code example for the UDB-based SPI module.

Regards,

Noriaki

I can reproduce the phenomenon on my PSoC 5LP board by modifying the SPI_Design project example.

It seems that the following context does not work as you expected.

while ((SPIM_ReadTxStatus() & SPIM_STS_TX_FIFO_EMPTY) != SPIM_STS_TX_FIFO_EMPTY );

In the SPI Master component datasheet, it was described as follows.

This means that this bit does not indicate the status of the software FIFO on the RAM area.  It just indicates the status of the hardware FIFO contained in UDBs.  So, no data bytes are sent to slave and the GetRxBufferSize() returns ZERO.

If you want to detect "the transmit from master is completed" as you write in the comment, SPIM_STS_SPI_DONE bit should be used.

while ((SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE) != SPIM_STS_SPI_DONE);

The GetRxBufferSize() returns 7 not 10.  This is because the size of software buffer is set to 8 in the project example.

If the software buffer sizes are increased to 16 for all combinations of SPIM/SPIS and RX/TX, the GetRxBufferSize() returns 10 meaning 10 elements are stored in the software FIFO.

Please refer attached project.

Regards,

Noriaki

Simon,

Maybe you see following description in the component datasheet.

It just says "Tx FIFO empty" and also says "for more information, see Status Register Bits."

In the "Status Register Bits" section I found a strange description regarding the Tx FIFO Empty.

I suppose that "no data bytes are sent to slave" because the SPI clock frequency is very low and the CPU is going to write data bytes too quickly.

Regards,

Noriaki

Hi,

Since this topic seemed to be very interesting,

I downloaded Noriaki-san's sample and tried with my CY8CKIT-059.

As I don't have LCD I added following lines to see the result.

Meantime, I suspected that as you were not using Rx_buffersize anywhere in the source code.

I used it to call my dump_data() function, so that it will not be optimized out by the compiler.

When I hit the assignment line of Rx_buffersize, naturally Rx_buffersize was 0,

as it was not assigned.

But when I stepped over the line, at the next statement,

Rx_buffersize was still ZERO.

Then finally when I hit the line where I called my dump_data() with Rx_buffersize as an argument.

The Rx_buffersize has value of 0x0000000A!

And in my TeraTerm the log was shown

So I believe that Rx_buffersize was actually assigned,

but somehow until it will be used, the debugger reported the value as ZERO.

moto