9 Replies Latest reply on Jul 16, 2019 7:54 PM by YuxianL_01

    SPI. Relationship between Tx FIFO, Tx Buffer, Rx FIFO & Rx Buffer


      I am confused with the relationship between Tx FIFO, Tx Buffer, Rx FIFO & Rx Buffer. Please correct me if my understanding of this is incorrect.


      In SPI, I am sending data from master to slave.


      Data (suppose 10 characters) from master will be filled into Tx Buffer. Then it will move into Tx FIFO, which in hardware is 4 bytes. Then the data will be received by slave in Rx FIFO, move into Rx Buffer and being saved. After all data being received (Rx FIFO Empty), Rx Buffer size should be 10 because I transmitted 10 characters