Hello folks and PSoCians,
I am currently on the way creating a custom PCB for the PSoC 6,
I have a slightly problem here. I didn't find a drawing for the reconmended land pattern like in the files for Cypress Sram 48 BGA https://www.cypress.com/file/42851/download.
I struggle at the moment with the following.
Cypress provided a Library with the PSoC 63 116 BGA with partnumbers which are not correctly fitting. ( Thank You for that. its awesome, has some cosmetics but is awesome )
The ball diameter of the part itself ( stated in the file PSoC 63 with BLE datasheet https://www.cypress.com/file/385921/download ) is 0.3mm plus minus 0.05 mm with a pitch of 0.5 mm
Thats so far clear.
For what I know from working with FPGAs the land should be 0.27 mm with a opening of 0.25mm ( so the ball form a miniature barrelshape )
In the footprint provided we have a land pattern with 0.3 mm.
If You look the 48 BGA land pattern it has 0.25mm balls ( plus minus 0.05 mm standard tolerance) and a 0.24mm land pattern size.
I know that also the difference of pitch is there. 0.5 mm PSoC, 0.75mm Memory BGA.
Maybe it makes sense but the biggest issue is that i can not fanout or route it so its able to manufacture it.
I needed to go down to a clearence of 0.07mm, via size 0.2 mm hole 0.1mm, trace width 0.12 mm.
This is just too little for be manufactureable in a normal way. I need to increase the via size and also track width.
Also i looked up specs for other BGA parts out there with similar grid and ball sizes. There is recomended 0.07 mm clearence, via size 0.25, hole 0.15 and trace 0.15 mm, but there are the pads also about 0.25 mm, ( if i reduce from 0.3 to 0.25 it gives around 0.5 mm more headroom so clearence about 0.08 and track width about 0.15 )
So what should I do.
So maybe You understand the struggle which i am stuck in.
Many greetings
Thomas
