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Following figure is about WDT of PSoC 4000 / PSoC 4000S / 4100S and PSoC Analog Coprocessor in cy_lfclk_v1_20.
I think the figure I think this figure explains that the WDT can reset directly.
But, there is not Watchdog at WDT setting in PSoC creator.
How can I set WDT to reset directly?
Best Regards,
Inoue
Solved! Go to Solution.
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Please refer to the "LFCLK Configuration Panels" table in the component datasheet of "PSoC 4 Low-Frequency Clock (cy_lfclk) 1.20".
it says that there are 4 WDT modes and "Watchdog (w/ interrupts) - Generates an interrupt on a match event and generates a reset on a 3rd unversed interrupt.
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Hi,
I think wdt causes reset whenever it is enabled and not cleared by the time it expires.
I tried to make a simple reset sample with TSoC CY8C4146LQI-S433 board (the Tora-gi board).
If you enter "sw" it causes software reset
and if you enter "wdt" it causes watch dog reset after a few seconds.
Note: wdt does not happen during we run debugger, so please try without debugger.
part of main.c
===================
void print_reset_cause(void)
{
uint32_t value ;
// value = CY_SYS_RES_CAUSE_REG ;
print("\nReset reason: ") ;
if (CY_SYS_RESET_WDT == CySysGetResetReason(CY_SYS_RESET_WDT)) {
print("WDT") ;
} else if (CY_SYS_RESET_PROTFAULT == CySysGetResetReason(CY_SYS_RESET_PROTFAULT)) {
print("Protection Violation") ;
} else if (CY_SYS_RESET_SW == CySysGetResetReason(CY_SYS_RESET_SW)) {
print("Software") ;
} else {
print("Unknown") ;
}
print("\n") ;
}
void disable_wdt(void)
{
CY_SYS_WDT_DISABLE_KEY_REG = 0xACED8865 ;
}
void enable_wdt(void)
{
CY_SYS_WDT_DISABLE_KEY_REG = 0x0000 ;
}
void init_hardware(void)
{
disable_wdt() ;
UART_SpiUartClearRxBuffer() ;
UART_SpiUartClearTxBuffer() ;
UART_ClearRxInterruptSource(UART_GetRxInterruptSource()) ;
uart_rx_int_ClearPending() ;
uart_rx_int_StartEx(usr_isr) ;
UART_Start() ;
CyGlobalIntEnable; /* Enable global interrupts. */
}
void do_command(char *cmd)
{
str2upper(cmd) ;
if (strcmp(cmd, "WDT") == 0) {
enable_wdt() ;
} else if (strcmp(cmd, "SW") == 0) {
CySoftwareReset() ;
} else {
print("Unknown command: ") ;
print(cmd) ;
print(" ignored\n") ;
}
}
int main(void)
{
init_hardware() ;
print_reset_cause() ;
splash() ;
prompt() ;
for(;;) {
if (get_str() > 0) {
do_command(str) ;
prompt() ;
}
}
}
===================
moto
P.S. I have not implemented clearing WDT before expires, once "wdt" is entered, it does reset.
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Please refer to the "LFCLK Configuration Panels" table in the component datasheet of "PSoC 4 Low-Frequency Clock (cy_lfclk) 1.20".
it says that there are 4 WDT modes and "Watchdog (w/ interrupts) - Generates an interrupt on a match event and generates a reset on a 3rd unversed interrupt.
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Please refer the "PSoC 4100S Family PSoC 4 Registers TRM, Document No. 002-10523" at the WCO_WDT_CONFIG register.
There is a 2-bit field WDT_MODE1 selecting the mode of the WDT operation. It is described that the mode 0x2 and 0x3 are "Not supported" on this device. This is why this device does not have the "Watchdog (w/o Interrupt" mode.
Regards,
Noriaki
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Thank you for all answer.
I understood that PSoC4100S can not be set "Watchdog (w/o Interrupt)" mode.[
Best Regards,
Inoue