CCG3PA Flash FW update using host controller using SWD programming / CC line Interface

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PrM_1403381
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Hello everyone,

We are using CCG3PA in our design, so we need to update the CCG3PA device Firmware, As per the CCG3PA Datasheet(002-16951) Page No.10

There are two ways to program application firmware into a CCG3PA device:

1. Programming the device flash over SWD Interface

2. Application firmware update over CC interface.

I have attached a image about initial design of CCG3PA application FW update, Please refer the attachment.

So my initial plan was to use SWD Programming based on AN84858 - PSoC 4 Programming Using an External Microcontroller (HSSP).

https://www.cypress.com/documentation/application-notes/an84858-psoc-4-programming-using-external-mi...

In the Programmer place used Cypress FX3, as shown in figure-1, I used GPIO Bit bang method for SWD programming, But the AN84858 says One of the important requirements is to ensure that the frequency of SWDCK clock line is at least 1.5 MHz to meet the acquire window timing. By using FX3 we are not able  achieve this. In Github a link to PSoc Programming using FX2LP, So i thouht of using FX3 as a host programmer (https://github.com/ghent360/PSOC4_swd_programmer ).

--> Can you suggest is it possible to implement SWD programming in Cypress FX3 GPIO Bit bang method ?

In figure-2, I mentioned one more approach for CCG3PA application FW update using another PSOC (For Example : PSoC - X).

In this case Cypress FX3 will be the host and it will get the .hex file data from the PS over USB, PSoC-X will the interface between Cypress FX3 and CCG3PA, PSOC-X should be able to get the data from Cypress FX3 over I2C PSoC-X(I2C Slave) and then send the data over GPIO's which i need to use as SWD_DATA and SWD_CK.

can you suggest any low end PSoC in that we can implement SWD programming master.

In figure - 2, I have mentioned connecting CC line of the PSoC - X to the CCG3PA and it will perform PD negotiation with CCG3PA, and enter into the FW update mode using unstructured VDM's (As per PD Spec).

To achieve this, I may need to change the PSoC - X(Programmer) FW to get the .hex file data (In AN84858 an hex file parser application is provided by cypress) for the target device and need to form an unstructured VDM's for sending FW update data to the CC3PA(Target) device. Any constraints do i need to take care?

NOTE : In place of PSoC - X which PSoC device can be used to achieve either of the programming methods ( SWD Programming / Over CC line interface), and it should be able to receive the data from the Cypress FX3 over I2C. (For SWD programming we can use available Miniprog-3, But we need to have our own programmer device within our design)

CCG3PA_Programming_Using_Host_Programmer.jpg

Thanks & Best Regards

Prasanna

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1 Solution

Hi Prasanna,

You can achieve a Maximum GPIO toggle frequency of SYSCLK/8 with a Complex GPIO .

 

Attached is  a simple demo project in which I have configured 4 GPIO as complex GPIO . The GPIO 0,1,2 & 3 are the GPIOs used and they are running at 48Mhz , 32Mhz, 24Mhz and 19.2Mhz. respectively.

Best Regards,

Lisa

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7 Replies
ShifangZ_26
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Hi Prasanna,

Kindly refer below comments:

1. Can you suggest is it possible to implement SWD programming in Cypress FX3 GPIO Bit bang method ?

>> FX3 GPIO can support up to 100MHz, so that the answer is YES, you can.

2. Can you suggest any low end PSoC in that we can implement SWD programming master.

>> Since the AN84858 - PSoC 4 Programming Using an External Microcontroller (HSSP) have example code and have been verified, PSoC4 on CYKITS - 042/040/042-BLE/044. The part number can be refer below lists, you could select is as per your requirements -- Received packages from FX3. But this is only for SWD programming. PSoCX cannot support to CC bootloader. CC bootloader host have to implemented PD, which is only can be achieved by CCGx device.

pastedImage_19.png

3. In figure - 2, I have mentioned connecting CC line of the PSoC - X to the CCG3PA and it will perform PD negotiation with CCG3PA, and enter into the FW update mode using unstructured VDM's (As per PD Spec).

>>You can use CYPD4126 to implement CC bootloader and SWD (porting the example code from PSoC 4).

Best Regards,

Lisa

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Hi Lisa,

Thanks for the response and the inputs provided. Kindly find my comments below.

1. Can you suggest is it possible to implement SWD programming in Cypress FX3 GPIO Bit bang method ?

>> FX3 GPIO can support up to 100MHz, so that the answer is YES, you can.

---------> With the above analysis i have chosen FX3 and tried to achieve 1.5MHz GPIO toggle for SWD Clock, Below is the outcome of Cypress FX3 GPIO,

If I use CyU3PGpioSetValue I am able to achieve 490 KHz, for this I referred the cypress community link : Increasing Frequency of Bit-Banged GPIO Clock in EZ-USB® FX3™ - KBA90267 , and followed the methods mentioned, and here is the outcome.

-> If I use CyU3PGpioSimpleSetValue Gpio toggle clock frequency achieved is 750KHz

-> With GPIO_SIMPLE register accessing method 1.27MHz, I have attached the clock capture image.

Can you suggest any other method for Cypress FX3's GPIO controlling for SWD CLOCK at 1.5 MHz ?

3. In figure - 2, I have mentioned connecting CC line of the PSoC - X to the CCG3PA and it will perform PD negotiation with CCG3PA, and enter into the FW update mode using unstructured VDM's (As per PD Spec).

>>You can use CYPD4126 to implement CC bootloader and SWD (porting the example code from PSoC 4).

----------> Thank you, we also selected the above mentioned Device, and I have ported SWD Programming to the CYPD4126, But I am facing an issue with register accessing method of GPIO's, Where can I get TRM for GPIO accessing using Registers.

Thanks & Regards

Prasanna

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Hi Praasanna,

1. This question have been mentioned in your previous threads: CCG3PA Flash programming using Cypress FX3 GPIO (SWD Programming) . May I know whether you have been tested the way in the KBA already? Is there any test results comes back?

2. The GPIO usage is same as PSoC4, since CCGx is Cortex-M0 also. You can use the example code directly. The TRM of CCG4 can be found in the link: https://www.cypress.com/documentation/technical-reference-manuals/ccg4-family-ez-pd-ccg4-registers-t...

https://www.cypress.com/documentation/technical-reference-manuals/ccg4-family-ez-pd-ccg4-registers-t...

https://www.cypress.com/documentation/technical-reference-manuals/ccg4-family-ez-pd-ccg4-architectur...

Best Regards,

Lisa

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Hi Lisa,

Thanks for the response,

I have mentioned the outcome of the KBA Document for toggle the GPIO, In the above response itself. Here is the outcome.

---------> With the above analysis i have chosen FX3 and tried to achieve 1.5MHz GPIO toggle for SWD Clock, Below is the outcome of Cypress FX3 GPIO,

If I use CyU3PGpioSetValue I am able to achieve 490 KHz, for this I referred the cypress community link : Increasing Frequency of Bit-Banged GPIO Clock in EZ-USB® FX3™ - KBA90267 , and followed the methods mentioned, and here is the outcome.

-> If I use CyU3PGpioSimpleSetValue Gpio toggle clock frequency achieved is 750KHz

-> With GPIO_SIMPLE register accessing method 1.27MHz.

Thanks

Prasanna

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Hi Prasanna,

Kindly refer the example code in the Threads: GPIO Toggling frequency related

Best Regards,

Lisa

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Hi Lisa,

I am not able to access the link you provided.

I received an error message "Access to this place or content is restricted. If you think this is a mistake, please contact your administrator or the person who directed you here.". Screen shot is attached.

Cyprees_Community.JPG

Thanks

Prasanna

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Hi Prasanna,

You can achieve a Maximum GPIO toggle frequency of SYSCLK/8 with a Complex GPIO .

 

Attached is  a simple demo project in which I have configured 4 GPIO as complex GPIO . The GPIO 0,1,2 & 3 are the GPIOs used and they are running at 48Mhz , 32Mhz, 24Mhz and 19.2Mhz. respectively.

Best Regards,

Lisa

0 Likes