PWM Implementation doesn't support full duty cycle

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anwic_3068166
Level 1
Level 1

Not sure if I am missing something but the PWM implementation doesn't appear support the full duty cycle range i.e. 0% and 100%.

I am about to utilise the Kill input to force the PWM to 0 when it's compare value is set to 0 when the compare logic set to <= (in order to get 100% duty cycle at compare value 255; 8-bit variant).

I thought I would ask this forum before adding this level of complexity.

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1 Solution

Antony,

I have another suggestion.

Suggestion:

  • Make sure that the period is at least 1 count lower than the maximum value allowed.
  • Set compare mode to PWM_x__B_PWM__LESS_THAN.  This will allow glitch-free 0%.
  • When you want glitch-free 100%, set the compare value to the period value +1.  Since the compare is higher than the period and the compare mode is '<' only, the output should be 100% glitch-free.

I have verified this approach.  It works!

Len

Len
"Engineering is an Art. The Art of Compromise."

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5 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Antony,

The PWM is fully capable of 0% and 100% duty cycle.  However, there is 'trick'.

If you need 0% to be fully 'OFF', you need to make sure the the compare value is 0 and the compare mode set to PWM_x__B_PWM__LESS_THAN.

If you need 100% to be fully 'ON', you need to make sure the the compare value is equal to the period and the compare mode set to PWM_x__B_PWM__LESS_THAN_OR_EQUAL.

You can see if you need to 0% and 100% support without output glitching, you need to change the compare mode appropriately.

Len

Len
"Engineering is an Art. The Art of Compromise."
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Thanks Len.  I hadn't thought of changing the mode on detecting an input demand of maximum.

Saves me having to use control registers as my UDBs are almost all gone.

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Antony,

I have another suggestion.

Suggestion:

  • Make sure that the period is at least 1 count lower than the maximum value allowed.
  • Set compare mode to PWM_x__B_PWM__LESS_THAN.  This will allow glitch-free 0%.
  • When you want glitch-free 100%, set the compare value to the period value +1.  Since the compare is higher than the period and the compare mode is '<' only, the output should be 100% glitch-free.

I have verified this approach.  It works!

Len

Len
"Engineering is an Art. The Art of Compromise."

Hi Len

I tried to change the compare mode dynamically but there is no function.

However, your second suggestion worked thanks.  I set the PWM period to 254 and have the PWM setup as LESS THAN compare and it then drives 0 at 0 compare value and 1 at 255 compare value.

Thanks for the help.

Tony

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Tony,

If you mark my second suggestion post as "Correct", I will get credit for it.  Thanks.

Len

Len
"Engineering is an Art. The Art of Compromise."
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