Reliability of SRAM with ECC

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My questions are regarding the CY7C1381KVE33 (flow through SRAM with ECC, 18Mbits):

- What is the failure rate of the CY7C1381KVE33? Please confirm it takes into account the probability for the ECC function to fail.
- Can Cypress provide a FMEDA (Failure Mode, Effect and Diagnostic Analysis)?
- Can Cypress provide a factory test coverage rate?
- Suppose that for some reason, the ECC mechanism fails in such a way that any stored data, even corrupted, is considered as good, and is consequenty NOT corrected.
Is such a failure possible?
- Is there any means for the application to check that the ECC function actually works?

Thanks a lot,

Frédéric.

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PradiptaB_11
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500 replies posted 250 solutions authored 250 replies posted

Hi,

Please find our comments below.

- What is the failure rate of the CY7C1381KVE33? Please confirm it takes into account the probability for the ECC function to fail.

Current failure rate for this platform is 11FITs based on our reliability monitor program and takes into account all failure modes

- Can Cypress provide a FMEDA (Failure Mode, Effect and Diagnostic Analysis)?

We did not perform FMEDA on this parts

- Can Cypress provide a factory test coverage rate?

We typically cover 95% of tests on this parts

- Suppose that for some reason, the ECC mechanism fails in such a way that any stored data, even corrupted, is considered as good, and is consequently NOT corrected. Is such a failure possible?

The ECC is implemented in combination logic and decodes the snapshot of the stored memory cells. If there is a SET event that calculation might get corrupted is the event hit the combination logic.This probability is very low on this technology. In similar technology devices we have found 5 orders of magnitude lower failure rates between logic and RAM cells.

- Is there any means for the application to check that the ECC function actually works?”

Yes, we have test modes to enable/disable ECC on the chip. So the idea would be to disable ECC -> inject error -> validate Error -> enable ECC -> read error address and confirm corrected

Thanks,

Pradipta.

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8 Replies
PradiptaB_11
Moderator
Moderator
Moderator
500 replies posted 250 solutions authored 250 replies posted

Hi,

Please find our comments below.

- What is the failure rate of the CY7C1381KVE33? Please confirm it takes into account the probability for the ECC function to fail.

Current failure rate for this platform is 11FITs based on our reliability monitor program and takes into account all failure modes

- Can Cypress provide a FMEDA (Failure Mode, Effect and Diagnostic Analysis)?

We did not perform FMEDA on this parts

- Can Cypress provide a factory test coverage rate?

We typically cover 95% of tests on this parts

- Suppose that for some reason, the ECC mechanism fails in such a way that any stored data, even corrupted, is considered as good, and is consequently NOT corrected. Is such a failure possible?

The ECC is implemented in combination logic and decodes the snapshot of the stored memory cells. If there is a SET event that calculation might get corrupted is the event hit the combination logic.This probability is very low on this technology. In similar technology devices we have found 5 orders of magnitude lower failure rates between logic and RAM cells.

- Is there any means for the application to check that the ECC function actually works?”

Yes, we have test modes to enable/disable ECC on the chip. So the idea would be to disable ECC -> inject error -> validate Error -> enable ECC -> read error address and confirm corrected

Thanks,

Pradipta.

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Hi Pradipta,

Thanks for your reply.

You wrote "Yes, we have test modes to enable/disable ECC on the chip".

Please could you give me details on how to activate/inhibit these test modes. I can't see anything about it in the CY7C1381KVE33 datasheet.

Many thanks,

Frédéric.

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Hi,

it is confidential information. We can share this with you after a NDA is in place.

Thanks,

Pradipta.

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Hi Pradipta,

Could you please just tell me if the test modes are available on the field (our purpose would be to test the ECC feature at each board’ start-up), or if it is only available at the factory, with specific voltages, tools, etc.?

Many thanks.

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Hi

In order to provide the special instruction for the test mode we need to have NDA in place.It does not require special equipment etc, but the system needs to be flexible enough to perform it in the field. Once we have NDA in place we can share details. The pins involved are pins that are also used in standard operation. I hope this clarifies your query.

Thanks,

Pradipta.

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Hi Pradipta,

Thank you for your mail, this is very clear. We are going to sign an NDA with Cypress.

Once the NDA is signed, could you tell me how to contact Cypress for technical questions?

Thank you,

Best regards

Frédéric Bonnin.

De : PradiptaB_11

Envoyé : lundi 27 mai 2019 12:00

À : BONNIN Frederic (SAFRAN ELECTRONICS & DEFENSE) <frederic.bonnin@safrangroup.com>

Objet : Re: - Reliability of SRAM with ECC

<http://www.cypress.com>

Cypress Developer Community <https://community.cypress.com/?et=watches.email.thread>

Reliability of SRAM with ECC

reply from PradiptaB_11<https://community.cypress.com/people/PradiptaB_11?et=watches.email.thread> in SYNC SRAM - View the full discussion<https://community.cypress.com/message/197213?et=watches.email.thread#197213>

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Hi,

You can always use the community forum for all the queries. You will always be supported for all the queries by all means.

Thanks,

Pradipta.

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Thank you Pradipta.

Regards,

Frédéric.

De : PradiptaB_11

Envoyé : mardi 28 mai 2019 11:44

À : BONNIN Frederic (SAFRAN ELECTRONICS & DEFENSE) <frederic.bonnin@safrangroup.com>

Objet : Re: - Reliability of SRAM with ECC

<http://www.cypress.com>

Cypress Developer Community <https://community.cypress.com/?et=watches.email.thread>

Reliability of SRAM with ECC

reply from PradiptaB_11<https://community.cypress.com/people/PradiptaB_11?et=watches.email.thread> in SYNC SRAM - View the full discussion<https://community.cypress.com/message/197373?et=watches.email.thread#197373>

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