PSOC 4 Timing Violation

[RoJa_1564316]

Hello,

my simple DCC decoder project gives a

"Warning-1367: Hold time violation found in a path from clock ( Clock_1(FFB) ) to clock ( \Bit_Timer:cy_m0s8_tcpwm_1\/tr_compare_match )."

which I don't understand.

My project:

The top DFF samples 80usec after a rising edge the DCC line

and the DFF below generates the according clock.

Its clk is fed by the negative cc signal, to be shure,

that DCC_Data is stable.

After 100usec, DCC_Clk is brought to LOW.

Static Timing Analysis in attachment.

[Bob_Marlowe]

I would suggest to put a "Sync" component into the cc path to avoid the timing issue.

Bob

[RoJa_1564316]

Thank you Bob,

but this only results in a another warning:

"Warning-1350: Asynchronous path(s) exist from "Clock_1(FFB)" to "Clock_1". See the timing report for details."

I must say that despite these warnings, I can see the right signals on pins DCC_Data and DCC_Clk on my logic analyzer.

I only feel uncomfortable with these warnings, as if they could incur some instabilities.

I also observe that the warnings also depend on routing to pins:

if I add output pins to cc and ov to watch on my LA,

warnings change or some times even vanish.

I guess that this something to do with different

routings of signals leading to different

timing calculations. It even changes when using different pin numbers.

Rolf

[odissey1 · Accepted solution]

Rolf,

Try to set pins sync settings to single-sinc / double-sinc (input / output tabs).

/odissey1