1 2 Previous Next 24 Replies Latest reply on May 29, 2019 1:16 PM by BoTa_264741 Go to original post
      • 15. Re: Filter-ADC-VDAC Sample & Hold


        I don't understand what you a trying to achieve with this DelSig modulator staff, and why it needs data input at 960kHz rate? Do you want convert analog wave into digital 1-bit stream, operating at 960kHz frequency?      


        as to the code snippet below, the flag_DtrReady being fired at sample rate of 48kHz. Then LPFilter reads CReg32 at 960kHz, multiplying stream rate 20x times.

        if (flag_DtrReady)



                    Filter_Result = 128u + Filter_1_Read8(Filter_1_CHANNEL_A);



        • 16. Re: Filter-ADC-VDAC Sample & Hold

          With the DelSig modulator I can reach a SNR over 90 dB and will end up with a better quality DAC.

          This is the way I'm implementing it on Matlab. Consider an input x with 16 bit values:


          The code snippet in MATLAB implements a 3rd ordem Sigma Delta Modulator:


          Vref = 256;




          e(i)=y(i)*Vref - x(i-1);

          x(i)=vin(i) - (3*e(i) - 3*e(i-1) + e(i-2));


          vin is the value that comes from the filter at 48 kHz.

          With this, I will end up with an output y quantized for 8 bits, but this should be processed under 960 kHz so I can process each value that comes from the ADC 20 times... and then I could actually integrate this with your interpolation method.

          Here's a Matlab plot comparing the DAC with and without the modulator.

          Sorry if this sounds confusing and thanks a lot for your help.



          • 17. Re: Filter-ADC-VDAC Sample & Hold


            this is interesting staff, which I am not familiar with. Do you have any links with more info on DelSig modulator?


            • 18. Re: Filter-ADC-VDAC Sample & Hold

              This is another approach for data interpolation (upsampling), which potentially can be done in PSoC5 hardware:

              Quadratic fits are entirely inappropriate for DSP

              • 19. Re: Filter-ADC-VDAC Sample & Hold

                /odissey1, sorry for the huge delay.
                Thanks a lot for the help and for all the tips! I have no documentation regarding DelSig modulator. I asked my advisor if he could send me some, but he also has to search for it. I can still send you the Matlab code I'm using. I think it's pretty easy to understand.

                • 20. Re: Filter-ADC-VDAC Sample & Hold


                  I learned a bit about upsampling and Del-Sig modulator since last time, and believe they are different things. The upsampling is a process of staffing more data points between original data. For example, 20x upsampling of 48kHz, results in 960kHz output update rate. This doesn't improve VDAC resolution. PSoC5 has 8-bit VDAC only, so no matter what, the THD will be no better than ~48dB.


                  Another thing is improving VDAC resolution (e.g from 8-bit to 16-bit). Here Delta-Sigma modulator can help (theoretically). Basically, instead of writing VDAC output register value N, we update it between N-1, N and N+1 at high speed (as controlled by the D-S modulator). The time-averaged VDAC output will be of higher resolution. In practice this doesn't work that well, because of 8-bit VDAC hardware imperfections INL/DNL). Previous experiments using PSoC5 showed that 9-10-bits is the the practical limit for a slow signals. With high-speed signals (~1MHz), situation is much worse as PSoC5 VDAC certified only to about 100kHz. Above this threshold, VDAC starts showing bit-flipping glitches (xxx1 0000 <-> 0000 1111), and actual resolution decreases.


                  I drafted some Verilog code for 2-nd order Delta-Sigma modulator, but not tested it with VDAC yet. Keep in mind that to achieve higher resolution, the VDAC update rate form the Modulator must be likely 20-200x faster than desired output rate. If after interpolator it was 960kHz, now it needs approx 20-200MHz, which is not feasible with PSoC5 VDAC hardware.


                  I have no idea what is going to happen if both upsampling and Delta-Sigma frequencies made to coincide. To be honest, I don't know how to measure 90dB THD using a standard 8-bit scope.


                  Hope that somehow clarifies the problem.


                  • 21. Re: Filter-ADC-VDAC Sample & Hold

                    Do you know if those bit-flipping glitches occur in frequencies above 20 kHz? Because this is for an audio device, so if those glitches are not present in between the audio spectra, it won't cause any trouble to me.
                    Do you think you can provide that Verilog code for the 2nd order Delta-Sigma?

                    Thank you!

                    • 22. Re: Filter-ADC-VDAC Sample & Hold


                      I will provide Delta-Sigma modulator demo over weekends. It is still "in progress".

                      PSoC5 VDAC8 bit-flipping demo screenshot is provided below. For full sine (0-255) is gives 16 glithes per period. If VDAC sampling rate >1MHz, a LP filter is necessary. This is hardware issue specific to PSoC5, for example PSoC4 (IDAC8) has almost no glitches.


                      • 23. Re: Filter-ADC-VDAC Sample & Hold


                        Attached is DelSig Modulator example project, which includes both 1-st order and 2-nd order modulator examples on separate pages. Disable current page before switching to another one to avoid error messages. The 1-st order modulator seems to work OK. The 2-nd order modulator needs more testing. To tune VDAC output, a shaft rotary encoder was used, the Encoder library can be found here:

                        Quad Decoder with Button Switch component for rotary shaft encoders


                        Another custom library was used for annotation:

                        Annotation library for CY8CKIT-059 Prototyping Kit


                        The DSM component  provided as-is, more testing and verification required. The output of the DSM can be routed to VDAC by the bus or DMA. The modulator has 8 fixed and 14 fractional bits (22-bit total), which is overkill for the 8-bit DAC, it can be simplified further to save PLD resources. It is unlikely to obtain better than 10-11 bits from VDAC8 anyways.



                        • 24. Re: Filter-ADC-VDAC Sample & Hold

                          Here is an article which, I believe, describes the intended target design. Not sure if it is doable in PSoC though:


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