Regarding EZ-USB FX3 Kit, FPGA and GPIF II.

[moab_1649426]

Hi, I am using the EZ-USB FX3 Kit to get data from an FPGA to a host computer through GPIF II.

The design on the FPGA is pretty simple, the handshaking between the FX3 kit and the FPGA achieved by only two control signals: RESET and WRITE_ENABLE, and the PCLK signal as clock source for the FPGA at 80 MHz.

The data transfer rate is only 40 MB/S.

The firmware on the FX3 Kit is "GPIF_Example2.img" from the downloadable examples related to "SupperSpeed Device by Example" book, and on the host computer I use the "CollectData.exe" program which also come with the book's examples.

"CollectData" triggers the RESET signal and start the state-machine on the FPGA, the FPGA's design then asserts eventually the WRITE_ENABLE signal once every 8 clocks to trigger the state-machine of the GPIF II to save the 32 bit value into a DMA buffer and send it to the host computer, and that what the first example should do if I understood the example!

The problem is as flowing:

case 1 : When I upload the firmware into the FX3 kit and run the "CollectData" application to Start Data Transfer, the application receives 1048576 bytes of unknown data of value of "0xEF" then ‭‭16384‬ bytes of correct data from the FPGA is received followed by another 1032192‬ bytes of value of "0xEF" , and repeatedly the application receive the same data pattern (1048576 bytes of value of 0xEF and 16384‬ bytes of correct data, 1032192‬ bytes of value of "0xEF").

case 2 : In every attempt to Start Data Transfer again, the "CollectData" application receive only that strange value of "0xEF" !!!

only when I reset the FX3 Kit and upload the firmware again I got the same result as in case 1.

I used a logic analyzer to make sure that the FPGA design works correctly so please advice me what can I do to make the firmware works correctly every time, and to get correct data, not that dummy "0xEF" ?

Thank you in advance for any help.

Regards

[SrinathS_16]

Hello,

- Please let me know if you tested using the Cypress USB Control Center application.

- When the FPGA is not sending data, what is the state of the data lines?

- When there is no read request from the host, is the PCLK still active?

Best regards,

Srinath S

[moab_1649426]

Hello Srinath S,

When the FPGA is not sending any data a fixed marking value of 0xBAADBEEF is the output of the FPGA's data lines.

for now the PCLK is always active.

I did not test the firmware using Cypress USB Control Center app. because I could not figure it out how to send control request and in receive data from a Bulk in endpoint in the same time. Is there any document in that regards?

Best Regards

[SrinathS_16 · Accepted solution]

Hello,

- The firmware is such that it samples the DQ[31:0] lines as long as there is PCLK signal. In the example, the clock source is set as internal and so the clock is provided continuously. In your case, since you have mentioned that the clock signal is always present, the FX3 samples the data lines DQ[31:0] throughout. To stop sampling the data, either the GPIO17 pin needs to be pulled HIGH or the PCLK signal must be cut off. This will eliminate the additional unwanted bytes of data being received.

- Since, you have mentioned that FPGA is sending a fixed value of 0xBAADBEEF, the same should be received on the application when there is no active transfer. Kindly, probe the data lines DQ[31:0] and check if this data is being received.

- To understand using the Control Center, please refer to the CyControlCenter.PDF document in the following path after FX3 SDK installation.

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\SuiteUSB

Best regards,

Srinath S